Expand menu
Hello, Sign in
My Account
0
Cart
Home
Products
Sensors
Semiconductors
Passive Components
Connectors
Power
Electromechanical
Optoelectronics
Circuit Protection
Integrated Circuits - ICs
Main Products
Manufacturers
Blog
Services
About OMO
About Us
Contact Us
Check Stock
74HC4020N,652
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
74HC_HCT4020
All information pr
ovided in this d
ocument is subje
ct to legal discla
imers.
© NXP B.V
. 2012. All rights rese
rved.
Product data sheet
Rev
. 5 — 6 August 2012
10 of 20
NXP Semiconductors
74HC4020; 74HCT4020
14-st
age binary ripple c
ounter
Measurement points are given in
T
able 8
.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 9.
W
aveforms sh
owing the output Qn to out
put Qn+1 prop
agation delays
001aai120
Qn output
t
PLH
t
PHL
V
OH
V
OH
V
OL
V
OL
V
M
V
M
Qn+1 output
T
able 8.
Mea
surement points
Ty
p
e
Input
Output
V
M
V
M
74HC4020
0.5
V
CC
0.5
V
CC
74HCT4020
1.3 V
1.3 V
74HC_HCT4020
All information pr
ovided in this d
ocument is subje
ct to legal discla
imers.
© NXP B.V
. 2012. All rights rese
rved.
Product data sheet
Rev
. 5 — 6 August 2012
1
1 of 20
NXP Semiconductors
74HC4020; 74HCT4020
14-st
age binary ripple c
ounter
T
est data is given in
T
able 9
.
Definitions test circuit:
R
T
= T
ermination resistance should be equal t
o output impedance Z
o
of the pulse generator
.
C
L
= Load capacitance including jig and probe cap
acitance.
Fig 10.
T
est circuit for me
asuring switching tim
es
001aah768
t
W
t
W
t
r
t
r
t
f
V
M
V
I
negative
pulse
GND
V
I
positive
pulse
GND
10 %
90 %
90 %
10 %
V
M
V
M
V
M
t
f
V
CC
DUT
R
T
V
I
V
O
C
L
G
T
able 9.
T
est da
t
a
Ty
p
e
Input
Load
V
I
t
r
, t
f
C
L
74HC4020
V
CC
6 ns
15 pF
, 50 pF
74HCT4020
3 V
6 ns
15 pF
, 50 pF
74HC_HCT4020
All information pr
ovided in this d
ocument is subje
ct to legal discla
imers.
© NXP B.V
. 2012. All rights rese
rved.
Product data sheet
Rev
. 5 — 6 August 2012
12 of 20
NXP Semiconductors
74HC4020; 74HCT4020
14-st
age binary ripple c
ounter
13. Package
outline
Fig 1
1.
Package outline
SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
SOT38-4
95-01-14
03-02-13
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w
M
b
1
b
2
e
D
A
2
Z
16
1
9
8
E
pin 1 index
b
0
5
10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT
A
max.
12
b
1
(1)
(1)
(1)
b
2
cD
E
e
M
Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min.
A
max.
b
max.
w
M
E
e
1
1.73
1.30
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
0.254
2.54
7.62
8.25
7.80
10.0
8.3
0.76
4.2
0.51
3.2
inches
0.068
0.051
0.021
0.015
0.014
0.009
1.25
0.85
0.049
0.033
0.77
0.73
0.26
0.24
0.14
0.12
0.01
0.1
0.3
0.32
0.31
0.39
0.33
0.03
0.17
0.02
0.13
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P20
74HC4020N,652
Mfr. #:
Buy 74HC4020N,652
Manufacturer:
NXP Semiconductors
Description:
Counter Shift Registers 14-STAGE BINARY
Lifecycle:
New from this manufacturer.
Delivery:
DHL
FedEx
Ups
TNT
EMS
Payment:
T/T
Paypal
Visa
MoneyGram
Western
Union
Products related to this Datasheet
74HCT4020N,652
74HC4020N,652