74HC_HCT4020 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 6 August 2012 7 of 20
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
11. Dynamic characteristics
I
CC
supply current V
I
= V
CC
or GND; I
O
=0A;
V
CC
=5.5V
- - 8.0 - 80 - 160 A
I
CC
additional
supply current
V
I
=V
CC
2.1 V; I
O
=0A;
other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V
pin MR - 110 396 - 495 - 539 A
pin CP
- 85 306 - 383 - 417 A
C
I
input
capacitance
-3.5- - - - -pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC4020
t
pd
propagation
delay
CP to Q0; see Figure 8
[1]
V
CC
= 2.0 V; C
L
= 50 pF - 39 140 - 175 - 210 ns
V
CC
= 4.5 V; C
L
= 50 pF - 14 28 - 35 - 42 ns
V
CC
= 5.0 V; C
L
=15pF - 11 - - - - - ns
V
CC
= 6.0 V; C
L
= 50 pF - 11 24 - 30 - 36 ns
Qn to Qn+1; see Figure 9
V
CC
= 2.0 V; C
L
=50pF - 22 75 - 95 - 110 ns
V
CC
= 4.5 V; C
L
=50pF - 8 15 - 19 - 22 ns
V
CC
= 5.0 V; C
L
=15pF - 6 - - - - - ns
V
CC
= 6.0 V; C
L
=50pF - 6 13 - 16 - 19 ns
t
PHL
HIGH to LOW
propagation
delay
MR to Qn; see Figure 8
V
CC
=2.0 V; C
L
= 50 pF - 55 170 - 215 - 225 ns
V
CC
= 4.5 V; C
L
= 50 pF - 20 34 - 43 - 51 ns
V
CC
= 5.0 V; C
L
=15pF - 17 - - - - - ns
V
CC
= 6.0 V; C
L
= 50 pF - 16 29 - 37 - 43 ns
t
t
transition
time
Qn; see Figure 8
[2]
V
CC
= 2.0 V; C
L
=50pF - 19 75 - 95 - 110 ns
V
CC
= 4.5 V; C
L
=50pF - 7 15 - 19 - 22 ns
V
CC
= 6.0 V; C
L
=50pF - 6 13 - 16 - 19 ns
74HC_HCT4020 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 6 August 2012 8 of 20
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
t
W
pulse width CP HIGH or LOW;
see Figure 8
V
CC
= 2.0 V; C
L
= 50 pF 80 14 - 100 - 120 - ns
V
CC
= 4.5 V; C
L
=50pF 16 4 - 20 - 24 - ns
V
CC
= 6.0 V; C
L
=50pF 14 3 - 17 - 20 - ns
MR HIGH; see Figure 8
V
CC
= 2.0 V; C
L
= 50 pF 80 17 - 100 - 120 - ns
V
CC
= 4.5 V; C
L
=50pF 16 6 - 20 - 24 - ns
V
CC
= 6.0 V; C
L
=50pF 14 5 - 17 - 20 - ns
t
rec
recovery time MR to CP; see Figure 8
V
CC
= 2.0 V; C
L
=50pF 50 6 - 65 - 75 - ns
V
CC
= 4.5 V; C
L
=50pF 10 2 - 13 - 15 - ns
V
CC
= 6.0 V; C
L
=50pF 9 2 - 11 - 13 - ns
f
max
maximum
frequency
see Figure 8
V
CC
= 2.0 V; C
L
= 50 pF 6.0 30 - 4.8 - 4.0 - MHz
V
CC
= 4.5 V; C
L
=50pF 30 92 - 24 - 20 - MHz
V
CC
= 5.0 V; C
L
= 15 pF - 101 - - - - - MHz
V
CC
= 6.0 V; C
L
= 50 pF 35 109 - 28 - 24 - MHz
C
PD
power
dissipation
capacitance
[3]
-19- - - - - pF
74HCT4020
t
pd
propagation
delay
CP to Q0; see Figure 8
[1]
V
CC
= 4.5 V; C
L
= 50 pF - 18 36 - 45 - 54 ns
V
CC
= 5.0 V; C
L
= 15 pF - 15 - - - - - ns
Qn to Qn+1; see Figure 9
V
CC
= 4.5 V; C
L
=50pF - 8 15 - 19 - 22 ns
V
CC
= 5.0 V; C
L
=15pF - 6 - - - - - ns
t
PHL
HIGH to LOW
propagation
delay
MR to Qn; see Figure 8
V
CC
= 4.5 V; C
L
= 50 pF - 22 45 - 56 - 68 ns
V
CC
= 5.0 V; C
L
=15pF - 19 - - - - - ns
t
t
transition
time
Qn; see Figure 8
[2]
V
CC
= 4.5 V; C
L
=50pF - 7 15 - 19 - 22 ns
t
W
pulse width CP HIGH or LOW;
see Figure 8
V
CC
= 4.5 V; C
L
=50pF 20 7 - 25 - 30 - ns
MR HIGH; see Figure 8
V
CC
= 4.5 V; C
L
=50pF 20 8 - 25 - 30 - ns
t
rec
recovery time MR to CP; see Figure 8
V
CC
= 4.5 V; C
L
=50pF 10 2 - 13 - 15 - ns
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT4020 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 6 August 2012 9 of 20
NXP Semiconductors
74HC4020; 74HCT4020
14-stage binary ripple counter
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
= C
PD
V
CC
2
f
i
+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
12. Waveforms
f
max
maximum
frequency
see Figure 8
V
CC
= 4.5 V; C
L
=50pF 25 47 - 20 - 17 - MHz
V
CC
= 5.0 V; C
L
=15pF - 52 - - - - - MHz
C
PD
power
dissipation
capacitance
[3]
-20- - - - - pF
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. Clock timing, propagation delays, pulse widths and measurement points

74HC4020N,652

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Counter Shift Registers 14-STAGE BINARY
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet