MAX395
Serially Controlled, Low-Voltage,
8-Channel SPST Switch
8 _______________________________________________________________________________________
Note 1: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 2: ∆R
ON
= R
ON(max)
- R
ON(min)
. On-resistance match between channels and on-resistance flatness are guaranteed only with
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
Note 3: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
Note 4: Guaranteed by design.
Note 5: Leakage testing at single supply is guaranteed by testing with dual supplies.
Note 6: See Figure 6. Off isolation = 20log
10
V
COM
/V
NO
, V
COM
= output. NO = input to off switch.
Note 7: Between any two switches. See Figure 3.
TIMING CHARACTERISTICS—Single +3V Supply (Figure 1)
(V+ = +3.0V to +3.6V, V- = 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
SERIAL DIGITAL INTERFACE
RESET Minimum Pulse Width t
RW
105 nsT
A
= +25°C
Allowable Fall Time at DIN,
SCLK (Note 4)
t
SCF
2 µs
20% of V+ to 70% of V+,
C
L
= 10pF
C, E, M
Fall Time of DOUT (Note 4) t
DF
300 ns
20% of V+ to 70% of V+,
C
L
= 10pF
C, E, M
Rise Time of DOUT (Note 4) t
DR
300 ns
20% of V+ to 70% of V+,
C
L
= 10pF
C, E, M
Allowable Rise Time at DIN,
SCLK (Note 4)
t
SCR
2 µs
20% of V+ to 70% of V+,
C
L
= 10pF
C, E, M
DIN Data Valid after Falling SCLK
(Note 4)
t
DO
400
ns
Data Hold Time (Note 4)
Data Setup Time (Note 4) t
DS
200 38 ns
t
DH
0 -38
150
50% of SCLK to 10% of
DOUT, C
L
= 10pF
SCLK Low Time (Note 4)
ns
t
CL
C, E, M
190 ns
T
A
= +25°C
C, E, M
C, E, M
PARAMETER SYMBOL
MIN TYP MAX
(Note 2)
UNITS
C, E, M
SCLK High Time (Note 4)
CS Lag Time (Note 4) t
CSH2
240 ns
t
CH
190
CS Lead Time (Note 4)
Cycle Time (Note 4)
SCLK Frequency f
SCLK
ns
0 2.1 MHz
t
CH
+t
CL
480
t
CSS
240 ns
C, E, M
ns
C, E, M
C, E, M
C, E, M
C, E, M
CONDITIONS
