IS62C5128BL-45QLI-TR

Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. B
06/28/2011
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specication and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specication before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to signicantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS62C5128BL, IS65C5128BL
FEATURES
High-speed access time: 45ns
Low Active Power: 50 mW (typical)
Low Standby Power: 10 mW (typical)
CMOS standby
TTL compatible interface levels
Single 5V ± 10% power supply
Fully static operation: no clock or refresh
required
Available in 32-pin sTSOP-I, 32-pin SOP and
32-pin TSOP-II packages
Commercial, Industrial and Automotive tem-
perature ranges available
Lead-free available
DESCRIPTION
The ISSI IS62C5128BL and IS65C5128BL are high-speed,
4,194,304-bit static RAMs organized as 524,288 words by
8 bits. They are fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times as
fast as 45ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62C5128BL and IS65C5128BL are packaged in the
JEDEC standard 32-pin sTSOP-I, 32-pin SOP and 32-pin
TSOP-II packages
FUNCTIONAL BLOCK DIAGRAM
JULY 2011
512K x 8 HIGH-SPEED CMOS STATIC RAM
A0-A18
CE
OE
WE
512K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
IS62C5128BL, IS65C5128BL
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
06/28/2011
32-pin sTSOP (TYPE I)  32-pin SOP
32-pin TSOP (TYPE II) 
PIN DESCRIPTIONS
A0-A18 Address Inputs
CE Chip Enable 1 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
Vdd Power
GND Ground
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
A18
A15
V
DD
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
V
DD
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. B
06/28/2011
IS62C5128BL, IS65C5128BL
CAPACITANCE
(1,2)
Symbol  Parameter  Conditions  Max. Unit
Cin Input Capacitance Vin = 0V 6 pF
Cout Output Capacitance Vout = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
a = 25°C, f = 1 MHz, Vdd = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol  Parameter  Test Conditions  Min. Max. Unit
Voh Output HIGH Voltage Vdd = Min., ioh = –1.0 mA 2.4 V
Vol Output LOW Voltage Vdd = Min., iol = 2.1 mA 0.4 V
Vih Input HIGH Voltage
(1)
2.2 Vdd + 0.5 V
Vil Input LOW Voltage
(1)
–0.3 0.8 V
ili Input Leakage GND Vin Vdd
Com. –1 1 µA
Ind. –2 2
Auto. –5 5
ilo Output Leakage
GND Vout Vdd Com. –1 1 µA
Outputs Disabled Ind. –2 2
Auto. –5 5
Note:
1.
Vill (min) = -2.0V AC (pulse width <10 ns). Not 100% tested.
Vihh (max) = Vdd + 2.0V AC (pulse width <10 ns). Not 100% tested.
TRUTH TABLE
I/O PIN
Mode  WE CE OE I/O0-I/O7  VDD Current 
Not Selected X H X High-Z isb1, isb2
Output Disabled H L H High-Z iCC1, iCC2
Read H L L dout iCC1, iCC2
Write L L X din iCC1, iCC2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol  Parameter  Value  Unit
Vterm Terminal Voltage with Respect to GND –0.5 to +7.0 V
tstg Storage Temperature –65 to +150 °C
Pt Power Dissipation 1.5 W
iout DC Output Current (LOW) 20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent dam-
age to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IS62C5128BL-45QLI-TR

Mfr. #:
Manufacturer:
ISSI
Description:
SRAM 4Mb (512k x 8) Async SRAM 5v
Lifecycle:
New from this manufacturer.
Delivery:
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