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HTF8C32_64_128x64HG.fm - Rev. E 6/08 EN
9 ©2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB: (x64, SR) 200-Pin DDR2 SDRAM SODIMM
Electrical Specifications
Table 10: DDR2 IDD Specifications and Conditions – 256MB
Values are for the MT47H32M8 DDR2 SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
Parameter/Condition Symbol -667 -53E -40E Units
Operating one bank active-precharge current;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0 720 640 600 mA
Operating one bank active-read-precharge current; I
OUT = 0mA; BL = 4,
CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data pattern is same as I
DD4W
I
DD1 800 720 680 mA
Precharge power-down current; All device banks idle;
t
CK =
t
CK (IDD); CKE
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
I
DD2P 40 40 40 mA
Precharge quiet standby current; All device banks idle;
t
CK =
t
CK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
IDD2Q 320 280 200 mA
Precharge standby current; All device banks idle;
t
CK =
t
CK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
IDD2N 320 280 240 mA
Active power-down current; All device banks open;
t
CK =
t
CK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Fast PDN Exit
MR[12] = 0
I
DD3P 240 200 160 mA
Slow PDN Exit
MR[12] = 1
48 48 48 mA
Active standby current; All device banks open;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
I
DD3N 400 320 240 mA
Operating burst write current; All device banks open, continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
DD4W 1,520 1,280 1,000 mA
Operating burst read current; All device banks open, continuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
I
DD4R 1,440 1,200 920 mA
Burst refresh current;
t
CK =
t
CK (IDD); Refresh the command at every
t
RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are switching
I
DD5 1,440 1,360 1,320 mA
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
DD6404040mA
Operating bank interleave read current; All device banks interleaving
reads, I
OUT = 0mA; BL = 4, CL = CL (IDD), AL =
t
RCD (IDD) - 1 ×
t
CK (IDD);
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RRD =
t
RRD (IDD),
t
RCD =
t
RCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching; See I
DD7 conditions for detail
I
DD7 2,080 1,920 1,840 mA
