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HTF8C32_64_128x64HG.fm - Rev. E 6/08 EN
4 ©2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB: (x64, SR) 200-Pin DDR2 SDRAM SODIMM
Module Pin Assignments and Descriptions
Table 7: Pin Descriptions
Symbol Type Description
A[15:0] Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and
auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA[2/1:0]) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE
command. A[12:0] (512MB) and A[13:0] (1GB, 2GB).
A[15:14] are connected for parity.
BA[2:0] Input
Bank address inputs: BA[2/1:0] define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA[2/1:0] define which mode register (MR, EMR1,
EMR2, and EMR3) is loaded during the LOAD MODE command. BA[1:0] (512MB, 1GB) and
BA[2:0] (2GB).
CK[1:0]
CK#[1:0]
Input
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
CKE0 Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry
and clocks on the DDR2 SDRAM.
DM[8:0] Input
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH, along with the input data, during a write access. DM is sampled on both edges
of DQS. Although the DM pins are input-only, DM loading is designed to match that of the DQ
and DQS pins.
ODT0 Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT
is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be
ignored if disabled via the LOAD MODE command.
RAS#, CAS#,
WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
RESET# Input
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can
be used during power-up to ensure that CKE is LOW and DQ are High-Z.
S0# Input
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
SA[1:0] Input
Serial address inputs: These pins are used to configure the SPD EEPROM address range on
the I
2
C bus.
SCL Input
Serial clock for SPD EEPROM: SCL is used to synchronize communication to and from the
SPD EEPROM.
DQ[63:0] I/O
Data input/output: Bidirectional data bus.
DQS[8:0],
DQS#[8:0]
I/O
Data strobe: DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command. Output with read data. Edge-aligned with read data. Input with write data.
Center-aligned with write data.
SDA I/O
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the
SPD EEPROM on the module on the I
2
C bus.
V
DD Supply
Power supply: 1.8V ±0.1V. The component V
DD are connected to the module VDD.
V
DDSPD Supply
SPD EEPROM power supply: +1.7V to +3.6V.
V
REF Supply
Reference voltage: V
DD/2.
V
SS Supply
Ground.
NC –
No connect: These pins are not connected on the module.
