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NCP1575DG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
NCP1575
http://onsemi.com
10
APPLICATION INFORMATION
THEORY OF OPERATION
The NCP1575 is a simple, synchronous, fixed−frequency,
low−voltage buck controller using the V
2
control method.
V
2
Control Method
The V
2
control method uses a ramp signal generated by
the ESR of the output capacitors. This ramp is proportional
to the ac current through the main inductor and is offset by
the dc output voltage. This control scheme inherently
compensates for variation in either line or load conditions,
since the ramp signal is generated from the output voltage
itself. The V
2
method differs from traditional techniques
such as voltage mode control, which generates an artificial
ramp, and current mode control, which generates a ramp
using the inductor current.
Figure 20. V
2
Control with Slope Compensation
COMP
Reference
Voltage
+
+
PWM
RAMP
Error
Amplifier
Error
Signal
Output
Voltage
V
FB
GATE(H)
GATE(L)
−
−
Slope
Compensation
The V
2
control method is illustrated in Figure 20. The
output voltage generates both the error signal and the ramp
signal. Since the ramp signal is simply the output voltage, it
is affected by any change in the output, regardless of the
origin of that change. The ramp signal also contains the DC
portion of the output voltage, allowing the control circuit to
drive the main switch from 0% to 100% duty cycle as
required.
A variation in line voltage changes the current ramp in the
inductor, which causes the V
2
control scheme to compensate
the duty cycle. Since any variation in inductor current
modifies the ramp signal, as in current mode control, the V
2
control scheme offers the same advantages in line transient
response.
A variation in load current will affect the output voltage,
modifying the ramp signal. A load step immediately changes
the state of the comparator output, which controls the main
switch. The comparator response time and the transition
speed of the main switch determine the load transient
response. Unlike traditional control methods, the reaction
time to the output load step is not related to the crossover
frequency of the error signal loop.
The error signal loop can have a low crossover frequency,
since the transient response is handled by the ramp signal
loop. The main purpose of this ‘slow’ feedback loop is to
provide dc accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be rolled
off at a low frequency. Enhanced noise immunity improves
remote sensing of the output voltage, since the noise
associated with long feedback traces can be effectively
filtered.
Line and load regulation are drastically improved because
there are two independent control loops. A voltage mode
controller relies on the change in the error signal to
compensate for a deviation in either line or load voltage.
This change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains a fixed error signal during
line transients, since the slope of the ramp signal changes in
this case. However, regulation of load transients still requires
a change in the error signal. The V
2
method of control
maintains a fixed error signal for both line and load variation,
since the ramp signal is affected by both line and load.
The stringent load transient requirements of modern
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope in the output ripple can
lead to pulse width jitter and variation caused by both random
and synchronous noise. A ramp waveform generated in the
oscillator is added to the ramp signal from the output voltage
to provide the proper voltage ramp at the beginning of each
switching cycle. This slope compensation increases the noise
immunity, particularly at duty cycles above 50%.
Startup
The NCP1575 features a programmable soft−start
function, which is implemented through the error amplifier
and the external compensation capacitor. This feature
prevents stress to the power components and limits output
voltage overshoot during startup. As power is applied to the
regulator, the NCP1575 undervoltage lockout circuit (UVL)
monitors the IC’s supply voltage (V
CC
). The UVL circuit
holds the GATE(H) output low and the GATE(L) output
high until V
CC
exceeds the 8.5 V threshold. A hysteresis
function of 1.0 V improves noise immunity. The
compensation capacitor connected to the COMP pin is
charged by a 30 A current source. When the capacitor
voltage exceeds the 0.465 V offset of the PWM comparator,
the PWM control loop will allow switching to occur. The
upper gate driver GATE(H) is activated, turning on the upper
MOSFET. The current ramps up through the main inductor
and linearly powers the output capacitors and load. When
the regulator output voltage exceeds the COMP pin voltage
minus the 0.465 V PWM comparator offset threshold and
the artificial ramp, the PWM comparator terminates the
initial pulse.
NCP1575
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11
Figure 21. Idealized Waveforms
8.5 V
0.465 V
V
IN
V
COMP
V
FB
GATE(H)
UVLO STARTUP NORMAL OPERATION
t
S
Normal Operation
During normal operation, the duty cycle of the gate drivers
remains approximately constant as the V
2
control loop
maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load conditions
will result in changes in duty cycle to maintain regulation.
Input Supplies
The NCP1575 can be used in applications where a 12 V
supply is available along with a lower voltage supply. Often
the lower voltage supply is 5 V, but it can be any voltage less
than the 12 V supply minus the required gate drive voltage
of the top MOSFET. The greater the difference between the
two voltages, the better the efficiency due to increasing V
GS
available to turn on the upper MOSFET. In order to maintain
power supply stability, the lower supply voltage should be
at least 1.5 times the desired voltage.
Adding a few additional components allows the NCP1575
to convert power in a “12 V only” application. This circuit
is illustrated in Figure 1. Note that in all cases, the maximum
supply voltage specification of 20 V must not be exceeded.
Gate Charge Effect on Switching Times
When using the onboard gate drivers, the gate charge has
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading.
Transient Response
The 200 ns reaction time of the control loop provides fast
transient response to any variations in input voltage and
output current. Pulse−by−pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.
Overvoltage Protection
Overvoltage protection is provided as a result of the
normal operation of the V
2
control method and requires no
additional external components. The control loop responds
to an overvoltage condition within 200 ns, turning off the
upper MOSFET and disconnecting the regulator from its
input voltage. This results in a crowbar action to clamp the
output voltage, preventing damage to the load. The regulator
remains in this state until the overvoltage condition ceases.
Shutdown
When the input voltage connected to V
CC
falls through the
lower threshold of the UVLO comparator, a fault latch is set.
The fault latch provides a signal that forces both GATE(H)
low and GATE(L) high, producing a low−impedance current
sink to ground at the converter switch node. At the same
time, the latch also turns on a transistor which pulls down on
the COMP pin, quickly discharging the external capacitor,
and allowing COMP to fall.
CONVERTER DESIGN
Choosing the V
OUT
Resistor Divider Values
The NCP1575 has an internal 0.98 V reference. A resistor
divider is used to set the output voltage.
R1
R2
V
OUT
V
FB
Figure 22.
The formula to set the output voltage is
V
OUT
(R1R2 1) (0.98 V)
Arbitrarily choose a value of R2 that is sufficiently low
that the V
FB
bias current (typically 50 nA) will have
negligible effect on the output voltage. Solve the equation
above for the value of R1.
Choosing the Oscillator Frequency
The NCP1575 has an oscillator that is trimmed to 200 kHz
at the factory. The NCP1575 will operate at this frequency
without the addition of any external components. However,
the oscillator is user−programmable with a single resistor.
This resistor is connected between the R
OSC
pin and ground.
Adding this resistor will raise the frequency above 200 kHz.
A graph of oscillator frequency vs. R
OSC
resistance is
provided in the typical operating characteristics section of
this data sheet.
Selection of the Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their Equivalent
NCP1575
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12
Series Resistance (ESR), and Equivalent Series Inductance
(ESL). For best transient response, a combination of low
value/high frequency and bulk capacitors placed close to the
load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
The voltage change during the load current transient is:
V
OUT
I
OUT
ESL
t
ESR
t
TR
C
OUT
where:
I
OUT
/ t = load current slew rate;
I
OUT
= load transient;
t = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
t
TR
= output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula:
ESR
MAX
V
ESR
I
OUT
where:
V
ESR
= change in output voltage due to ESR (assigned
by the designer)
Once the maximum allowable ESR is determined, the
number of output capacitors can be found by using the
formula:
Number of capacitors
ESR
CAP
ESR
MAX
where:
ESR
CAP
= maximum ESR per capacitor (specified in
manufacturer’s data sheet).
ESR
MAX
= maximum allowable ESR.
The actual output voltage deviation due to ESR can then
be verified and compared to the value assigned by the
designer:
V
ESR
I
OUT
ESR
MAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
ESL
MAX
V
ESL
t
I
Selection of the Input Inductor
A common requirement is that the buck controller must
not disturb the input voltage. One method of achieving this
is by using an input inductor and a bypass capacitor. The
input inductor isolates the supply from the noise generated
in the switching portion of the buck regulator and also limits
the inrush current into the input capacitors upon power up.
The inductor’s limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the load changes from no load to full load
(load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. The inductor successfully blocks the ripple current
while placing the transient current requirements on the input
bypass capacitor bank, which has to initially support the
sudden load change.
The minimum inductance value for the input inductor is
therefore:
L
IN
V
(dIdt)
MAX
where:
L
IN
= input inductor value;
V = voltage seen by the input inductor during a full load
swing;
(dI/dt)
MAX
= maximum allowable input current slew rate.
The designer must select the LC filter pole frequency so
that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double−pole network
with a slope of −2.0, a roll−off rate of −40 dB/dec, and a
corner frequency:
f
C
1
2 LC
where:
L = input inductor;
C = input capacitor(s).
Selection of the Output Inductor
There are many factors to consider when choosing the
output inductor. Maximum load current, core and winding
losses, ripple current, short circuit current, saturation
characteristics, component height and cost are all variables
that the designer should consider. However, the most
important consideration may be the effect inductor value has
on transient response.
The amount of overshoot or undershoot exhibited during
a current transient is defined as the product of the current
step and the output filter capacitor ESR. Choosing the
inductor value appropriately can minimize the amount of
energy that must be transferred from the inductor to the
capacitor or vice−versa. In the subsequent paragraphs, we
will determine the minimum value of inductance required
for our system and consider the trade−off of ripple current
vs. transient response.
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NCP1575DG

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Manufacturer:
ON Semiconductor
Description:
Switching Controllers Low Voltage Synchronous Buck
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