LT3032 Series
15
3032ff
For more information www.linear.com/LT3032
OUTN (Pin 7): Negative Output. This output supplies power
to the negative side load. A minimum output capacitor
of 1µF is required to prevent oscillations. Larger output
capacitors are required for applications with large tran-
sient loads to limit peak voltage transients. A parasitic
diode exists between OUTN and INN; OUTN can not be
pulled more negative than INN during normal operation,
or more than 0.5V below INN during a fault condition. See
the Applications Information section for more information
on output capacitance and bypass capacitors.
ADJN (Pin 8, Adjustable Part Only): Negative Adjust. This
is the input to the negative side error amplifier. The ADJN
pin has a typical bias current of 30nA that flows out of the
pin. The ADJN pin voltage is –1.22V referenced to ground,
and the output voltage range is –1.22V to –20V. A parasitic
diode exists between ADJN and INN. The ADJN pin cannot
be pulled more negative than INN during normal operation,
or more than 0.5V below INN during a fault condition.
SHDNN (Pin 10): Negative Shutdown. The SHDNN pin puts
the negative side into a low power shutdown state. The
SHDNN pin is referenced to ground for regulator control,
allowing the negative side
to be driven by either positive
or negative logic. The negative output will be off if the
SHDNN pin is within ±0.8V(typical) of ground. Pulling the
SHDNN pin more than –1.9V or +1.4V(typical) will turn the
negative output on. The SHDNN pin can be driven by 5V
logic or open-collector logic with a pull-up resistor. The
pull-up resistor is required to supply the pull-up current of
the open-collector device, normally several microamperes,
and the SHDNN pin current, typically 3µA out of the pin
(for negative logic) or 6µA into the pin (for positive logic).
If unused, the SHDNN pin must be connected to INN. The
negative output will be shut down if the SHDNN pin is open
circuit. A parasitic diode exists between SHDNN and INN,
the SHDNN pin cannot be pulled more negative than INN
during normal operation, or more than 0.5V below INN
during a fault condition.
PIN FUNCTIONS
BYPN (Pin 11): Negative Bypass. The BYPN pin is used
to bypass the reference of the negative side regulator to
achieve low noise performance. A small capacitor from
OUTN to this pin will bypass the reference to lower the
output voltage noise.
A maximum value of 0.01µF is used
for
reducing output voltage noise to a typical 30µV
RMS
over the 10Hz to 100kHz bandwidth. If not used, this pin
must be left unconnected.
SHDNP (Pin 12): Positive Shutdown. The SHDNP pin puts
the positive side into a low power shutdown state. The
positive output will be off when the SHDNP pin is pulled
below 0.6V(typical). The SHDNP pin can be driven by 5V
logic or open-collector logic with a pull-up resistor. The
pull-up resistor is required to supply the pull-up current
of the open-collector device, normally several microam
-
peres, and the SHDNP
pin current, typically 1µA into the
pin. If unused, the SHDNP pin must be connected to INP.
The positive output will be shut down if the SHDNP pin
is open circuit. The SHDNP pin can be tied directly to the
SHDNN pin and both pins driven directly by positive logic
for a single point control of both outputs.
NC (Pin 13/Pins 2, 8 for Fixed Voltage Devices): No
Connect. The No Connect pin has no connection to inter
-
nal cir
cuitry and may be tied to INP, GND, INN, SHDNP
,
SHDNN, OUTP, OUTN, floated, or tied to any other point.
INP (
Pin 14): Positive Input. Power is supplied to the
positive side of the LT3032 through the INP pin. A bypass
capacitor is required on this pin if it is more than six inches
away from the main input filter capacitor. In general, the
output impedance of a battery rises with frequency, so
it is advisable to include a bypass capacitor in battery-
powered circuits. A bypass capacitor in the range of 1µF
to 10µF is sufficient.
