LT3032EDE-3.3#PBF Datasheet LT3032IDE-5#PBF, LT3032EDE-12#PBF, LT3032EDE-15#PBF | P16-P18

LT3032 Series

3032ff

For more information www.linear.com/LT3032

The LT3032 is a dual 150mA positive and negative low noise

low dropout linear regulator with micropower quiescent

current and shutdown. It supplies ±150mA at a dropout

of 300mV. Output voltage noise can be lowered on the

positive side to 20µV

RMS

and to 30µV

RMS

on the negative

side over the 10Hz to 100kHz bandwidth with the addition

of 0.01µF reference bypass capacitors. Additionally, the

reference bypass capacitors improve transient response,

lowering the settling time for transient load conditions.

Quiescent current is 25µA for the positive side and –30µA

for the negative side (45µA each for the LT3032-12/

LT3032-15), typically dropping to less than 3µA total in

shutdown. In addition to the low quiescent current, the

LT3032 incorporates several protection features which

make it ideal for use in battery-powered systems. If the

load is common mode between the two outputs, it does

not matter which output starts first; either output can be

pulled to the opposing side of ground and the regulator

will still start and operate.

Setting Output Voltage

The adjustable LT3032 has output voltage ranges of 1.22V

to 20V for the positive side and –1.22V to –20V for the

negative side. The output voltages

are set by the ratio of

two external resistor dividers as shown in Figure 1. The

LT3032 servos the outputs to maintain the voltages at the

ADJP and ADJN pins to 1.22V and –1.22V, respectively.

The current in the bottom resistor of each divider (R1P

or R1N) is equal to 1.22V/R1 and the current in the top

resistor (R2P or R2N) is equal to the current in the bottom

resistor plus the respective ADJP/ADJN pin bias current.

The bias current for ADJP and ADJN is 30nA at 25°C,

flowing into the pin for ADJP and flowing out of the pin

for ADJN. The output voltages can then be calculated us

ing the

formulas shown in Figure 1. The value of R1P or

R1N

should be less than 250k to minimize errors in the

resultant output voltage caused by the ADJP/ADJN pin

bias current. Note that in shutdown the respective output

is turned off and the divider current will be zero. Curves

of ADJP Pin Voltage, ADJN Pin Voltage, ADJP Pin Bias

Current, and ADJN Pin Bias Current (all vs Temperature)

appear in the Typical Performance Characteristics.

The LT3032 is tested and specified

with the ADJP/ADJN

pin tied to the respective OUTP/OUTN pin and a ±5µA DC

load (unless otherwise specified) for an output voltage

of ±1.22V. Specifications for output voltages greater than

this will be proportional to ±1.22V; (V

OUT

/±1.22V). For

example, load regulation for an output current change

of 1mA to 150mA is –2mV typical at V

OUTN

= –1.22V. At

OUTN

= –12V, load regulation is:

(–12V/–1.22V)•(–2mV) = –19.6mV

Bypass Capacitors and Low Noise Performance

The LT3032 provides reasonable noise performance

without reference bypass capacitors from OUTP/OUTN

to the corresponding BYPP/BYPN pin. Using the LT3032

with the addition of reference bypass capacitors lowers

output voltage noise. Good quality low leakage capacitors

are recommended. These capacitors bypass the internal

references for the positive and negative sides of the LT3032,

providing low frequency noise poles. The noise poles

provided by the bypass capacitors decrease the output

voltage noise to as low as 20µV

RMS

for the positive side

and 30µV

RMS

for the negative side with the use of 0.01µF

bypass capacitors.

The BYPP pin and BYPN pin are high impedance nodes

and leakage into or out of these pins affects the reference

voltage. The BYPP pin operates

at approximately 74

mV at

Figure 1. Setting Output Voltages

APPLICATIONS INFORMATION

LT3032

OUTP

OUTN

R2P

R1P

R1N

R2N

ADJP

GND

ADJN

OUTN

3032 F01

OUTP

=1.22V 1+

R2P

R1P













+ I

ADJP

( )

R2P

( )

ADJP

=1.22V

ADJP

= 30nA at 25°C

OUTPUT RANGE= 1.22V TO 20V

OUTN

= –1.22V 1+

R2N

R1N













+ I

ADJN

( )

R2N

( )

ADJN

= –1.22V

ADJN

= –30nA at 25°C

OUTPUT RANGE= –1.22V TO – 20V

LT3032 Series

3032ff

For more information www.linear.com/LT3032

APPLICATIONS INFORMATION

25°C during normal operation where the BYPN pin oper-

ates at approximately –60mV. DC leakages on the order

1µA into or out of these pins can throw off the internal

reference by 20% or more.

Output Capacitance and Transient Response

The LT3032 requires output capacitors for stability. It

is designed to be stable with most low ESR capacitors

(typically ceramic, tantalum or low ESR electrolytic). A

minimum output capacitor of 2.2μF with an ESR of 3Ω

or less is recommended to prevent oscillations on each

output. The LT3032 is a micropower device and output

transient response is a function of output capacitance.

Larger values of output capacitance decrease peak devia

tions and provide improved transient response for larger

load current changes. Additional capacitors, used to de-

couple individual

components powered by the LT3032,

increase the effective output capacitor value. When using

bypass capacitors (for low noise operation), larger values

of output capacitors are needed. For 100pF of bypass ca

pacitance, 3.3µF of

output capacitance is recommended.

With a 330pF bypass capacitor or larger, a 4.7µF output

capacitor is recommended. The shaded region of Figure 2

defines the range over which the LT3032 is stable. The

minimum ESR needed is defined by the amount of bypass

capacitance

used, while the maximum ESR is 3Ω. These

requirements are applicable to both the positive and nega

tive linear regulator.

Give extra consideration to the use of ceramic capacitors.

Ceramic capacitors are manufactured with a variety of di

electrics, each with different behavior across temperature

and applied voltage. The most common dielectrics used

are specified with EIA temperature characteristic codes of

Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are

good for providing high capacitances in a small package,

but they tend to have strong voltage and temperature

coefficients as shown in Figures 3 and 4. When used with

a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an

effective value as low as 1μF to 2μF for the DC bias voltage

applied and over the operating temperature range. The X5R

and X7R dielectrics result in more stable characteristics

and are more suitable for use as the output capacitor.

The X7R type has better stability across temperature,

while the X5R is less expensive and is available in higher

values. Care still must be exercised when using X5R and

7R capacitors. The X5R and X7R codes only specify

operating temperature range and maximum capacitance

change over temperature. Capacitance change due to DC

bias with X5R and X7R capacitors is better than Y5V and

Z5U capacitors, but can still be significant enough to drop

capacitor values below appropriate levels. Capacitor DC

bias characteristics tend to improve as component case

size increases, but expected capacitance at operating

voltage should be verified in situ for a given application.

Voltage and temperature coefficients are not the only

sources of problems. Some ceramic capacitors have a

piezoelectric response. A piezoelectric device generates

voltage across its terminals due to mechanical stress. In

a ceramic capacitor, the stress can be induced by vibra

tions in

the system or thermal transients. Tapping on the

ceramic

bypass capacitor with a pencil generated the noise

shown in Figure 5. Similar vibration induced behavior can

masquerade as increased output voltage noise.

OUTPUT CAPACITANCE (µF)

ESR (Ω)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

3 10

1762 F02

2 4 5

7 8

STABLE REGION

BYP

= 330pF

BYP

≥ 3300pF

BYP

= 100pF

BYP

= 0

Figure 2. Stability

LT3032 Series

3032ff

For more information www.linear.com/LT3032

Stability and Input Capacitance

Low ESR, ceramic input bypass capacitors are acceptable

for applications without long input leads. However, applica

tions connecting a power supply to an LT3032’s circuit’s

INP/INN and GND pins with long input wires combined

with low ESR, ceramic input capacitors are prone to voltage

spikes, reliability concerns and application-specific board

oscillations. The input wire inductance found in many

battery-powered applications, combined with the low ESR

ceramic input capacitor, forms a high-Q LC resonant tank

circuit. In some instances this resonant frequency beats

against the output current dependent LDO bandwidth and

interferes with proper operation. Simple circuit modifica

tions/solutions are

then required. This behavior is not

indicative of LT3032 instability, but is a common ceramic

input bypass capacitor application issue.

The self-inductance, or isolated inductance, of a wire is

directly proportional to its length. Wire diameter is not a

major factor on its self-inductance. For example, the self-

inductance of a 2-AWG isolated wire (diameter = 0.26”) is

about half the self-inductance of a 30-AWG wire (diameter

= 0.01”). One foot of 30-AWG wire has about 465nH of

self-inductance.

One of two ways reduces a wire’s self-

inductance. One

method

divides the current flowing towards the LT3032

between two parallel conductors. In this case, the farther

apart the wires are from each other, the more the self-

inductance is reduced; up to a 50% reduction when placed

a few inches apart. Splitting the wires basically connects

two equal inductors in parallel, but placing them in close

proximity gives the wires mutual inductance adding to

the self-inductance. The second and most effective way

to reduce overall inductance is to place both forward and

return current conductors (the input and GND wires) in

very close proximity. Two 30-AWG wires separated by only

0.02”, used as forward– and return– current conductors,

reduce the overall self-inductance to approximately one-

fifth that of a single isolated wire.

APPLICATIONS INFORMATION

DC BIAS VOLTAGE (V)

CHANGE IN VALUE (%)

3032 F03

–20

–40

–60

–80

–100

2 6

X5R

Y5V

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

Figure 3. Ceramic Capacitor DC Bias Characteristics

TEMPERATURE (°C)

–50

–20

–40

–60

–80

–100

25 75

3032 F04

–25 0

50 100 125

Y5V

CHANGE IN VALUE (%)

X5R

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

Figure 4. Ceramic Capacitor Temperature Characteristics

OUTPUT SET TO 5V

3032 F05

Figure 5. Noise Resulting From Tapping on a Ceramic Capacitor

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

LT3032EDE-3.3#PBF

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Manufacturer:

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Description:

LDO Voltage Regulators Dual 200mA Positive/Negative, Low Noise, Low Dropout Linear Regulator

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LT3032EDE-3.3#PBF

LT3032EDE-3.3#PBF

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