71V67803S150PFGI8 Datasheet 71V67603S150PFGI, 71V67603S133BQGI, 71V67803S133BGG | P1-P3

FEBRUARY 2009

DSC-5310/07

Features

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256K x 36, 512K x 18 memory configurations

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Supports high system speed:

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

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LBO input selects interleaved or linear burst mode

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Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

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3.3V core power supply

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Power down controlled by ZZ input

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3.3V I/O supply (VDDQ)

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Packaged in a JEDEC Standard 100-pin thin plastic quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

Description

The IDT71V67603/7803 are high-speed SRAMs organized as

256K X 36, 512K X 18

3.3V Synchronous SRAMs

3.3V I/O, Burst Counter

Pipelined Outputs, Single Cycle Deselect

IDT71V67603/Z

IDT71V67803/Z

256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,

data, address and control registers. Internal logic allows the SRAM to

generate a self-timed write based upon a decision which can be left until

the end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V67603/7803 can provide four cycles of

data for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the LBO input pin.

The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-

pin thin plastic quad flatpack (TQFP), a 119 ball grid array (BGA) and a 165

fine pitch ball grid array (fBGA).

-A

Address Inputs Input Synchronous

Chip Enable Input Synchronous

, CS

Chip Selects Input Synchronous

Output Enable Input Asynchronous

Global Write Enable Input Synchronous

BWE

Byte Write Enable Input Synchronous

, BW

(1)

Individual Byte Write Selects Input Synchronous

CLK Clock Input N/A

ADV

Burst Address Advance Input Synchronous

ADSC

Address Status (Cache Controller) Input Synchronous

ADSP

Address Status (Processor) Input Synchronous

LBO

Linear / Interleaved Burst Order Input DC

ZZ Sleep Mode Input Asynchronous

I/O

-I/O

, I/O

-I/O

Data Input / Output I/O Synchronous

, V

DDQ

Core Power, I/O Power Supply N/A

Ground Supply N/A

5310 tbl 01

Pin Description Summary

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V67802.

6.42

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Symbol Pin Function I/O Active Description

-A

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the

rising edge of CLK and ADSC Low or ADSP Low and CE Low.

ADSC

Address Status

(Cache Controller)

I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is

used to load the address registers with new addresses.

ADSP

Address Status

(Processor)

I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is used to

load the address registers with new addresses. ADSP is gated by CE.

ADV

Burst Address

Advance

I LOW Synchronous Address Advance. ADV is an active LOW input that is used to advance the

internal burst counter, controlling burst access after the initial address is loaded. When the

input is HIGH the burst counter is not incremented; that is, there is no address advance.

BWE

Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW

-BW

. If BWE is LOW at the

rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is

HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.

-BW

Individual Byte

Write Enables

I LOW Synchronous byte write enables. BW

controls I/O

0-7

, I/O

, BW

controls I/O

8-15

, I/O

, etc.

Any active byte write causes all outputs to be disabled.

Chip Enable I LOW Synchronous chip enable. CE is used with CS

and CS

to enable the IDT71V67603/7803.

CE also gates ADSP.

CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this

input.

Chip Select 0 I HIGH Synchronous active HIGH chip select. CS

is used with CE and CS

to enable the chip.

Chip Select 1 I LOW Synchronous active LOW chip select. CS

is used with CE and CS

to enable the chip.

Global Write

Enable

I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW

on the rising edge of CLK. GW supersedes individual byte write enables.

I/O

-I/O

I/O

-I/O

Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are

registered and triggered by the rising edge of CLK.

LBO

Linear Burst Order I LOW Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst

sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a

static input and must not change state while the device is operating.

Output Enable I LOW Asynchronous output enable. When OE is LOW the data output drivers are enabled on the

I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-

impedance state.

Power Supply N/A N/A 3.3V core power supply.

DDQ

Power Supply N/A N/A 3.3V I/O Supply.

Ground N/A N/A Ground.

NC No Connect N/A N/A NC pins are not electrically connected to the device.

ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71V67603/7803 to its lowest power consumption level. Data retention is guaranteed in

Sleep Mode.

5310 tbl 02

Pin Definitions

(1)

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.42

IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges

Functional Block Diagram

A0–A17/18

ADDRESS

CLR

A1*

A0*

18/19

–A

256K x 36/

512K x 18-

BIT

MEMORY

ARRAY

INTERNAL

ADDRESS

BW4

BW3

BW2

BW1

Byte 1

Write Register

36/18

ADSP

ADV

CLK

ADSC

CS1

Byte 1

Write Driver

Byte 2

Write Driver

Byte 3

Write Driver

Byte 4

Write Driver

Byte 2

Write Register

Byte 3

Write Register

Byte 4

Write Register

BWE

LBO

I/O0–I/O31

I/OP1–I/OP4

DATA INPUT

36/18

OUTPUT

BUFFER

OUTPUT

Enable

Delay

Burst

Sequence

CEN

CLK EN

Burst

Logic

Binary

Counter

5301 drw 01

Powerdown

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

71V67803S150PFGI8

Mfr. #:

Buy 71V67803S150PFGI8

Manufacturer:

IDT

Description:

SRAM 9M 3.3V PBSRAM SLOW P/L

Lifecycle:

New from this manufacturer.

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71V67803S150PFGI8

71V67803S150PFGI8

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