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LTC2391CUK-16#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LTC2391-16
13
239116fa
APPLICATIONS INFORMATION
Internal Reference
To use the internal reference, simply tie the REFOUT and
REFIN pins together. This connects the 4.096V output of
the internal reference to the input of the internal reference
buffer. The output impedance of the internal reference is
approximately 2.6kΩ and the input impedance of the in-
ternal reference buffer is about 85kΩ. It is recommended
that this node be bypassed to ground with a 1μF or larger
capacitor to fi lter the output noise of the internal reference.
The REFSENSE pin should be left fl oating when using the
internal reference.
External Reference
An external reference can be used with the LTC2391-16
when even higher performance is required. The
LT1790-4.096 offers 0.05% (max) initial accuracy and
10ppm/°C (max) temperature coeffi cient. When using an
external reference, connect the reference output to the
REFIN pin and connect the REFOUT pin to ground. The
REFSENSE pin should be connected to the ground of the
external reference.
DYNAMIC PERFORMANCE
Fast fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2391-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 5 shows that the LTC2391-16 achieves
a typical SINAD of 93.5dB at a 250ksps sampling rate
with a 20kHz input.
Figure 5. 16k Point FFT of the LTC2391-16, f
S
= 250ksps, f
IN
= 20kHz
FREQUENCY (kHz)
0
–180
AMPLITUDE (dBFS)
–160
–120
–100
–80
50
100
125
0
239116 G08
–140
25 75
–60
–40
–20
SNR = 94dB
THD –103dB
SINAD = 93.5dB
SFDR = 104dB
LTC2391-16
14
239116fa
APPLICATIONS INFORMATION
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the fi rst fi ve harmonics and DC. Figure 5 shows
that the LTC2391-16 achieves a typical SNR of 94dB at a
250kHz sampling rate with a 20kHz input.
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (f
SMPL
/2).
THD is expressed as:
THD= 20log
V
2
2
+ V
3
2
+ V
4
2
...V
N
2
V
1
where V
1
is the RMS amplitude of the fundamental fre-
quency and V
2
through V
N
are the amplitudes of the second
through Nth harmonics.
POWER CONSIDERATIONS
The LTC2391-16 provides three sets of power supply
pins: the analog 5V power supply (AVP), the digital 5V
power supply (DVP) and the digital input/output interface
power supply (OVP). The fl exible OVP supply allows the
LTC2391-16 to communicate with any digital logic operating
between 1.8V and 5V, including 2.5V and 3.3V systems.
Power Supply Sequencing
The LTC2391-16 does not have any specifi c power supply
sequencing requirements. Care should be taken to observe
the maximum voltage relationships described in the Ab-
solute Maximum Ratings section. The LTC2391-16 has a
power-on reset (POR) circuit. With the POR, the result of
the fi rst conversion is valid after power has been applied
to the ADC. The LTC2391-16 will reset itself if the power
supply voltage drops below 2.5V. Once the supply voltage
is brought back to its nominal value, the POR will reinitial-
ize the ADC and it will be ready to start a new conversion.
Nap Mode
The LTC2391-16 can be put into the nap mode after a
conversion has been completed to reduce the power
consumption between conversions. In this mode some
of the circuitry on the device is turned off. Nap mode is
enabled by keeping CNVST low between conversions. When
the next conversion is requested, bring CNVST high and
hold for at least 250ns, then start the next conversion by
bringing CNVST low. See Figure 6.
Power Shutdown Mode
When PD is tied high, the LTC2391-16 enters power
shutdown and subsequent requests for conversion are
ignored. Before entering power shutdown, the digital
output data needs to be read. However, if a request for
power shutdown (PD = high) occurs during a conversion,
the conversion will fi nish and then the device will power
down. The data from that conversion can be read after PD
Figure 6. Nap Mode Timing for the LTC2391-16
CNVST
BUSY
NAP
t
CONV
t
ACQ
NAP MODE
239116 F06
t
5
LTC2391-16
15
239116fa
APPLICATIONS INFORMATION
= low is applied. In this mode, power consumption drops
to a typical value of 175μW from 95mW. This mode can
be used if the LTC2391-16 is inactive for a long period of
time and the user wants to minimize the power dissipation.
Recovery from Power Shutdown Mode
Once the PD pin is returned to a low level, ending the
power shutdown request, the internal circuitry will begin
to power up. If the internal reference is used, the 2.6kΩ
output impedance with the 1μF bypass capacitor on the
REFIN/REFOUT pins will be the main time constant for
the power-on recovery time. If an external reference is
used, typically allow 5ms for recovery before initiating a
new conversion.
Power Dissipation vs Sampling Frequency
The power dissipation of the LTC2391-16 will decrease
as the sampling frequency is reduced when nap mode
is activated. See Figure 7. In nap mode, a portion of the
circuitry on the LTC2391-16 is turned off after a conversion
has been completed. Increasing the time allowed between
conversions lowers the average power.
TIMING AND CONTROL
The LTC2391-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. CS and RD
control the digital interface on the LTC2391-16. When
either CS or RD is high, the digital outputs are high
impedance.
CNVST Timing
The LTC2391-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. Once a
conversion has been initiated, it cannot be restarted until
the conversion is complete. For optimum performance
CNVST should be a clean low jitter signal. Converter status
is indicated by the BUSY output which remains high while
the conversion is in progress. To ensure no errors occur
in the digitized results return the rising edge either within
40ns from the start of the conversion or wait until after
the conversion has been completed. The CNVST timing
needed to take advantage of the reduced power mode of
operation is described in the Nap Mode section.
Internal Conversion Clock
The LTC2391-16 has an internal clock that is trimmed
to achieve a maximum conversion time of 2500ns. No
external adjustments are required and with a maximum
acquisition time of 1485ns, a throughput performance of
250ksps is guaranteed.
DIGITAL INTERFACE
The LTC2391-16 allows both parallel and serial digital
interfaces. The fl exible OVP supply allows the LTC2391-16
to communicate with any digital logic operating between
1.8V and 5V, including 2.5V and 3.3V systems.
Figure 7. Power Dissipation of the LTC2391-16
Decreases with Decreasing Sampling Frequency
SAMPLING FREQUENCY (kHz)
10
POWER SUPPLY CURRENT (mA)
20
30
5
15
25
0.1 10 100 1000
239116 G15
0
1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

LTC2391CUK-16#PBF

Mfr. #:
Buy LTC2391CUK-16#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 5V 16-bit 250Ksps Int Ref Parallel / Serial SAR ADC in QFN-48
Lifecycle:
New from this manufacturer.
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