LTC2391-16
19
239116fa
APPLICATIONS INFORMATION
BOARD LAYOUT
To obtain the best performance from the LTC2391-16, a
printed circuit board (PCB) is recommended. Layout for
the printed circuit board should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals alongside analog signals or underneath
the ADC.
Recommended Layout
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1500A, the
evaluation kit for the LTC2391-16
Partial Schematic of Demoboard
BUSY
D15
D14
D13
D12
D11/SCLK
D10/SDOUT
D9/SDIN
D8
D7
D6
D5
D4
D3
D2
D1
D0
BYTESWAP
GND
BUSY
D15
D14
D13
D12
D11/SCLK
D10/SDOUT
D9/SDIN
D8
D7
D6
D5
D4
D3
D2
D1
D0
29
28
27
26
25
24
23
22
21
16
15
14
13
12
11
10
9
8
7
RD
30
CS
31
PD
33
RESET
REFOUT
3738
C36
F
3934
REFINREFSENSE
LTC2391-16
IN
+
IN
CNVST
CNVST
32
SER/PAR
4
GND
5
VCM
AVP/AVL AVP AVP AVP AVP
GND GND GND GND GND GND OGND
LTC2391-16
DVP OVP
18
3.3V
319
R24
1.0Ω
2
48 44 41 35 20 1 17
239116 TA02
40454647
DVP/DVL
36
43
R2
249Ω
1%
R3
249Ω
1%
44
C53
10μF
5V
C55
OPT
OB/2C
6
C40
4.7μF
C29
0.1μF
C28
10μF
C30
10μF
C31
0.1μF
C54
OPT
C2
2200pF
1206 NPO
LTC2391-16
20
239116fa
APPLICATIONS INFORMATION
Partial Top Silkscreen
Partial Layer 1 Component Side Partial Layer 2 Ground Plane
LTC2391-16
21
239116fa
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
7.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1
CHAMFER
C = 0.35
0.40 ±0.10
4847
1
2
BOTTOM VIEW—EXPOSED PAD
5.50 REF
(4-SIDES)
0.75 ±0.05
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UK48) QFN 0406 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
5.50 REF
(4 SIDES)
6.10 ±0.05 7.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
5.15 ±0.10
5.15 ±0.10
5.15 ±0.05
5.15 ±0.05
R = 0.10
TYP
UK Package
48-Lead Plastic QFN (7mm w 7mm)
(Reference LTC DWG # 05-08-1704 Rev C)

LTC2391CUK-16#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 5V 16-bit 250Ksps Int Ref Parallel / Serial SAR ADC in QFN-48
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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