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XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
I
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
F
EATURES
................................................................................................................................................... 1
A
PPLICATIONS
............................................................................................................................................. 1
Figure 1. Block Diagram of the XRT71D00 ........................................................................................... 1
Figure 2. Pin Out of the XRT71D00 (32 Lead TFQP Package) ............................................................. 2
ORDERING INFORMATION ............................................................................................... 2
TABLE OF CONTENTS...................................................................................................................................... I
PIN DESCRIPTIONS ........................................................................................................... 3
ELECTRICAL CHARACTERISTICS ................................................................................... 9
AC E
LECTRICAL
C
HARACTERISTICS
............................................................................................................. 9
Figure 3. Input/Output Timing ................................................................................................................ 9
M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMING
(
SEE
F
IGURE
4 ) ................................................................. 10
Figure 4. Timing Diagram for the Microprocessor Serial Interface .................................................. 10
SYSTEM DESCRIPTION ................................................................................................... 12
Figure 5. Illustration of the XRT71D00 (configured to operate in the “Hardware” Mode) ............ 12
Figure 6. Illustration of the XRT71D00 (configured to operate in the “Host” Mode) ...................... 13
1.0 The Jitter Attenuator PLL ...................................................................................................................... 13
1.1 THE JITTER TRANSFER CHARACTERISTICS OF THE JITTER ATTENUATOR PLL ..............................................................13
1.2 D
EFINITION OF JITTER................................................................................................................................................13
1.3 J
ITTER TRANSFER CHARACTERISTICS.........................................................................................................................13
Figure 7. Category 1 DS3 Jitter Transfer Mask .................................................................................. 14
1.3.1 Jitter Tolerance: ............................................................................................................................................14
1.3.2 Jitter Generation:...........................................................................................................................................14
1.3.3 Jitter Attenuation: ..........................................................................................................................................14
1.4 XRT71D00 JITTTER TRANSFER CHARACTERISTICS ....................................................................................................14
T
ABLE
1: XRT71D00 J
ITTER
T
RANSFER
F
UNCTION
.................................................................................. 15
T
ABLE
2: XRT71D00 J
ITTER
T
RANSFER
F
UNCTION
.................................................................................. 16
Figure 8. DS3 Jitter Transfer Characteristics ..................................................................................... 17
Figure 9. E3 Jitter Transfer Characteristics ........................................................................................ 17
Figure 10. STS-1 Jitter Transfer Characteristics ................................................................................ 18
T
ABLE
3: XRT71D00 M
AXIMUM
J
ITTER
T
OLERANCE
................................................................................. 19
T
ABLE
4: XRT71D00 M
AXIMUM
J
ITTER
T
OLERANCE
................................................................................. 20
2.0 Operating Mode ...................................................................................................................................... 21
2.1 HARDWARE MODE.....................................................................................................................................................21
T
ABLE
5: H
ARDWARE
M
ODE
P
IN
F
UNCTIONS
............................................................................................. 21
2.1.1 Host Mode:...................................................................................................................................................21
T
ABLE
6: A
DDRESS
AND
B
IT
F
ORMATS
OF
THE
C
OMMAND
R
EGISTERS
...................................................... 21
3.0 Microprocessor Serial Interface ............................................................................................................ 21
3.1 SERIAL INTERFACE OPERATION..................................................................................................................................21
3.1.1 Bit Descriptions .............................................................................................................................................21
3.2 READ OPERATION .....................................................................................................................................................22
3.3 W
RITE OPERATION....................................................................................................................................................22
Figure 11. Microprocessor Serial Interface Data Structure ............................................................... 22
3.4 SIMPLIFIED INTERFACE OPTION..................................................................................................................................22
Figure 12. Timing Diagram for the Microprocessor Serial Interface ................................................ 23
PACKAGE INFORMATION ............................................................................................... 24
32 LEAD TQFP PACKAGE DIMENSIONS ............................................................................................. 24
REVISIONS ....................................................................................................................... 25
ORDERING INFORMATION ................................................................................................................... 25
