XRT71D00
áç
áçáç
áç
E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
5
10
ClkES/(SDI) I
Clock Edge Select Input/Serial Data Input Pin.
The function of this pin depends on whether XRT71D00 is configured in Harware or
Host Mode.
Hardware Mode—Clock Edge Select Input
This input pin permits the user to do the following.
1.
To configure the XRT71D00 device to latch the data, on the RPOS and
RNEG input pin, upon either the rising or falling edge of the RCLK input
signal.
2.
To configure the XRT71D00 device to update the data, which is output via
the “RRPOS” and “RRNEG” pins, upon either the rising or falling edge of
the RRCLK output signal.
Setting this input pin LOW configures the XRT71D00 device to do the following.
1.
Sample and latch the RPOS and RNEG input signals upon the rising edge
of the RCLK input signal.
2.
Update the data, output via the RRPOS and RRNEG output pins, upon
the falling edge of the RRCLK output signal.
Conversely, setting this input pin HIGH configures the XRT71D00 device to do the fol-
lowing.
1.
Same and latch the RPOS and RNEG input signals upon the falling edge
of the RCLK input signal.
2.
Update the data, output via the RRPOS and RRNEG output pins, upon
the rising edge of the RRCLK output signal.
Host Mode—Serial Data Input
When the Microprocessor/Microcontroller is executing a READ operation, with the
Microprocessor Serial Interface (of the XRT71D00 device) then it is expected to apply
the address value (of the “Target” Command Register) to this input pin, in a serial man-
ner.
When the Microprocessor/Microcontroller is executing a WRITE operation, with the
Microprocessor Serial Interface, then it is expected to do the following.
1.
Apply the address value (of the “Target” Command Register) to this input
pin, in a serial manner.
2.
Apply the data (to be written into the “Target” Command Register) to this
input pin.
N
OTE
:
A detailed description on how to read and write data into the Command Regis-
ters of the XRT71D00 device (via the Microprocessor Serial Interface) is presented in
Section _.
11
FSS/(SClk) I
FIFO Size Select Input/Serial Clock Input.
The function of this input pin depends on whether XRT71D00 is configured in Hard-
ware or Host mode.
Hardware Mode—FIFO Size Select Input
This input pin permits the user to select the operating depth of the “on-chip” FIFO.
When high: Selects 32 bits FIFO.
When low: Selects 16 bits FIFO.
N
OTE
:
For SONET De-synchronizer applications, the user is advised to configure the
FIFO Depth to 32 bits.
Host Mode—Microprocessor Serial Interface Clock Signal
This signal will be used to sample the data, on the SDI pin, on the rising edge of this
signal. Additionally, during “Read” operations, the Microprocessor Serial Interface will
update the SDO output on the falling edge of this signal.
PIN DESCRIPTION
P
IN
#N
AME
T
YPE
D
ESCRIPTION
