Data Sheet AD5749
Rev. C | Page 25 of 28
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The PCB on which the AD5749 is
mounted should be designed so that the AD5749 lies on the
analog plane.
The AD5749 should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on each supply, located as close to the
package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capaci-
tor should have low effective series resistance (ESR) and low
effective series inductance (ESI) such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
In systems where there are many devices on one board, it is often
useful to provide some heat sinking capability to allow the power
to dissipate easily.
Figure 36. Paddle Connection to Board
The AD5749 has an exposed paddle beneath the device.
Connect this paddle to the GND of the AD5749. For optimum
performance, special considerations should be used to design
the motherboard and to mount the package. For enhanced
thermal, electrical, and board level performance, the exposed
paddle on the bottom of the package should be soldered to the
corresponding thermal land paddle on the PCB (GND).
Thermal vias should be designed into the PCB land paddle area
to further improve heat dissipation.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler® family of products from Analog Devices, Inc., provides
voltage isolation in excess of 5.0 kV. The serial loading structure
of the AD5749 makes it ideal for isolated interfaces because the
number of interface lines is kept to a minimum. Figure 37 shows a
4-channel isolated interface to the AD5749 using an ADuM1400.
For further information, visit http://www.analog.com/icouplers.
Figure 37. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5749 is via a serial bus that
uses a protocol compatible with microcontrollers and DSP proces-
sors. The communication channel is a 3-wire (minimum)
interface consisting of a clock signal, a data signal, and a
SYNC
signal. The AD5749 requires a 16-bit data-word with data valid
on the falling edge of SCLK.
AD5749
GND
PLANE
BOARD
0
8923-037
V
IA
V
OA
V
IB
V
OB
V
IC
V
OC
V
ID
V
OD
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
08923-038
SERIAL
CLOCK OUT
SERIAL
DATA OUT
SYNC OUT
CONTROL OUT
CONTROLLER
TO
SCLK
TO
SDIN
TO
SYNC
TO
CLEAR
ADuM1400
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD5749 Data Sheet
Rev. C | Page 26 of 28
OUTLINE DIMENSIONS
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
AD5749ACPZ −40°C to +105°C 32-Lead LFCSP CP-32-7
AD5749ACPZ-RL7 −40°C to +105°C 32-Lead LFCSP CP-32-7
1
Z = RoHS Compliant Part.
3.25
3.10 SQ
2.95
0.80
0.75
0.70
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
32
9
16
17
24
25
8
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.50
0.40
0.30
0.25 MIN
02-22-2017-A
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD
PKG-003898
SEATING
PLANE
EXPOSED
PAD
SIDE VIEW
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Data Sheet AD5749
Rev. C | Page 27 of 28
NOTES

AD5749ACPZ

Mfr. #:
Manufacturer:
Description:
Instrumentation Amplifiers IC PLC I DRIVER SGL-Supply 55V Max
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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