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AD5749ACPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
Data Sheet AD5749
Rev. C | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 4.
Parameter Rating
AVDD to GND −0.3 V to +58 V
DVCC to GND −0.3 V to +7 V
Digital Inputs to GND −0.3 V to DV
CC
+ 0.3 V, or 7 V
(whichever is less)
Digital Outputs to GND −0.3 V to DV
CC
+ 0.3 V, or 7 V
(whichever is less)
VREF to GND −0.3 V to +7 V
VIN to GND −0.3 V to +7 V
IOUT to GND −0.3 V to AV
DD
Operating Temperature Range
Industrial −40°C to +105°C
Storage Temperature Range
−65°C to +150°C
Junction Temperature (T
J
max) 125°C
32-Lead LFCSP Package
θ
JA
Thermal Impedance
1
42°C/W
Lead Temperature JEDEC industry standard
Soldering J-STD-020
1
Simulated data based on a JEDEC 2S2P test board with thermal vias.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
AD5749 Data Sheet
Rev. C | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
SDO/VFAULT
Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
This pin is a CMOS output.
2 CLRSEL In hardware or software mode, this pin selects the clear value, either zero scale or midscale. In software
mode, this pin is implemented as a logic OR with the internal CLRSEL bit.
3 CLEAR Active High Input. Asserting this pin sets the output current to zero-scale code or midscale of range
selected (user selectable). CLEAR is a logic OR with the internal CLEAR bit. See the Asynchronous Clear
(CLEAR) section for more details.
4 DVCC Digital Power Supply.
5 GND Ground Connection.
6
SYNC
/RSET Positive Edge-Sensitive Latch (
SYNC
). In software mode, a rising edge parallel loads the input shift
register data into the AD5749 and also updates the output.
Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current
sense resistor is used.
If RSET = 0, the external sense resistor is chosen.
If RSET = 1, the internal sense resistor is chosen.
7 SCLK/OUTEN Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling
edge of SCLK. This pin operates at clock speeds up to 50 MHz.
Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.
8 SDIN/R0 Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.
Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output
current range setting on the part.
9 AD2/R1 Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD0 and AD1, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output
current range setting on the part.
08923-004
NOTES
1. NC = NO CONNECT. CAN BE TIED TO GND.
2. DNC = DO NOT CONNECT.
3. THE EXPOSED PADDLE IS TIED TO GND.
24
DNC
23
DNC
22
GND
21
GND
20
DNC
19
DNC
18
IOUT
17
AVDD
1
2
3
4
5
6
7
8
SDO/VFAULT
CLRSEL
CLEAR
DVCC
GND
SYNC/RSET
SCLK/OUTEN
SDIN/R0
9
10
11
12
13
14
15
16
AD2/R1
AD1/R2
AD0/R3
REXT2
REXT1
VREF
VIN
GND
32
31
30
29
28
27
26
25
NC/IFAULT
FAULT/TEMP
RESET
HW SELECT
NC
NC
NC
NC
AD5749
TOP VIEW
(Not to Scale)
Data Sheet AD5749
Rev. C | Page 9 of 28
Pin No. Mnemonic Description
10 AD1/R2 Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD0 and AD2, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output
current range setting on the part.
11
AD0/R3
Device Addressing Bit (AD0). In software mode, this pin, in conjunction with AD1 and AD2, allows up to
eight devices to be addressed on one bus.
Range Decode Bit (R3). In hardware mode, this pin, in conjunction with R0, R1, and R2, selects the output
current range setting on the part.
12, 13 REXT2, REXT1 A 15 kΩ external current setting resistor can be connected between the REXT1 and REXT2 pins to
improve the IOUT temperature drift performance.
14 VREF Buffered Reference Input.
15 VIN Buffered Analog Input (0 V to 4.096 V).
16 GND Ground Connection.
17 AVDD Positive Analog Supply.
18 IOUT Current Output.
19, 20, 23, 24 DNC Do not connect to these pins.
21, 22 GND Ground Connection.
25, 26, 27, 28 NC No Connect. Can be tied to GND.
29 HW SELECT This part is used to configure the part to hardware or software mode.
HW SELECT = 0 selects software control.
HW SELECT = 1 selects hardware control.
30
RESET
In software mode, this pin resets the part to its power-on state. Active low.
In hardware mode, there is no reset. If using the part in hardware mode, the
RESET
pin should be tied high.
31 FAULT/TEMP Fault Alert (FAULT). In software mode, this pin acts as a general fault alert pin. It is asserted low when an
open-circuit, overtemperature error, or PEC interface error is detected. This pin is an open-drain output
and must be connected to a pull-up resistor.
Overtemperature Fault (TEMP). In hardware mode, this pin acts as an overtemperature fault pin. It is
asserted low when an overtemperature error is detected. This pin is an open-drain output and must be
connected to a pull-up resistor.
32 NC/IFAULT No Connect (NC). In software mode, this pin is a no connect. Instead, tie this pin to GND.
Open-Circuit Fault Alert (IFAULT). In hardware mode, this pin acts as an open-circuit fault alert pin. It is
asserted low when an open-circuit error is detected. This pin is an open-drain output and must be
connected to a pull-up resistor.
33 (EPAD) EPAD The exposed paddle is tied to GND.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

AD5749ACPZ

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