AD8133 Data Sheet
Rev. A | Page 16 of 17
OUTPUT PULL-DOWN
The output pull-down feature, when used in conjunction with
series Schottky diodes, offers a convenient means to connect a
number of AD8133 outputs together to form a video network.
The OPD pin is a binary input that controls the state of the
AD8133 outputs. Its binary input level is referenced to the most
positive power supply (see the Specifications tables for the logic
levels). When the OPD input is driven to its low state, the
AD8133 output is enabled and operates in its normal fashion. In
this state, the V
OCM
input can be used to provide a positive bias
on the series diodes, allowing the AD8133 to transmit signals
over the network. When the OPD input is driven to its high
state, the outputs of the AD8133 are forced to a low voltage,
irrespective of the level on the V
OCM
input, reverse-biasing the
series diodes and thus presenting high impedance to the
network. This feature allows a three-state output to be realized
that maintains its high impedance state even when the AD8133
is not powered. This condition can occur in KVM networks
where the AD8133s do not all reside in the same module, and
some modules in the network are not powered.
It is recommended that the output pull-down feature only be
used in conjunction with series diodes in such a way as to
ensure that the diodes are reverse-biased when the output pull-
down feature is asserted, since some loading conditions can
prevent the output voltage from being pulled all the way down.
KVM NETWORKS
In daisy-chained KVM networks, the drivers are distributed
along one cable and a triple receiver is located at one end.
Schottky diodes in series with the driver outputs are biased such
that the one driver that is transmitting video signals has its
diodes forward-biased and the disabled drivers have their
diodes reverse-biased. The output common-mode voltage, set
by the V
OCM
input, supplies the forward-biased voltage. When
the output pull-down feature is asserted, the differential outputs
are pulled to a low voltage, reverse-biasing the diodes.
In star networks, all cables radiate out from a central hub,
which contains a triple receiver. The series diodes are all located
at the receiver in the star network. Only one ray of the star is
transmitting at a given time, and all others are isolated by the
reverse-biased diodes. Diode biasing is controlled in the same
way as in the daisy-chained network.
In the daisy-chained and star networks that use diodes for
isolation, return paths are required for the common-mode
currents that flow through the series diodes. A common-mode
tap can be implemented at each receiver by splitting the100 Ω
termination resistor into two 50 Ω resistors in series. The diode
currents are routed from the tap between the 50 Ω resistors
back to the respective transmitters over one of the wires of the
fourth twisted pair in the UTP cable. Series resistors in the
common-mode return path are generally required to set the desired
diode current.
In point-to-point networks, there is one transmitter and one
receiver per cable, and the switching is generally implemented
with a crosspoint switch. In this case, there is no need to use
diodes or the output pull-down feature.
Diode and crosspoint switching are by no means the only type
of switching that can be used with the AD8133. Many other
types of mechanical, electromechanical, and electronic switches
can be used.
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
Standard high speed PCB layout practices should be adhered to
when designing with the AD8133. A solid ground plane is
recommended and good wideband power supply decoupling
networks should be placed as close as possible to the supply
pins. Small surface-mount ceramic capacitors are
recommended for these networks, and tantalum capacitors are
recommended for bulk supply decoupling.
AMPLIFIER-TO-AMPLIFIER ISOLATION
The least amount of isolation between the three amplifiers
exists between Amplifier A and Amplifier B. This is therefore
viewed as the worst-case isolation and is what is reflected in the
Specifications tables and Typical Performance Characteristics.
Refer to the Basic Test Circuit shown in Figure 33 for the test
conditions.
EXPOSED PADDLE (EP)
The LFCSP-24 package has an exposed paddle on the underside
of its body. In order to achieve the specified thermal resistance,
it must have a good thermal connection to one of the PCB
planes. The exposed paddle must be soldered to a pad on the
top of the board that is connected to an inner plane with several
thermal vias.
