ISL6263AIRZ Datasheet ISL6263AIRZ, ISL6263AIRZ-T, ISL6263ACRZ | P13-P15

FN9284.3

July 8, 2010

A severe overvoltage protection fault occurs immediately

after the voltage between the VO and VSS pins exceed the

rising severe-overvoltage threshold V

OVPS

, which is 1.545V,

the same reference voltage used by the VID DAC. The

ISL6263A will latch UGATE and PGOOD low but unlike other

protective faults, LGATE remains high until the voltage

between VO and VSS falls below approximately 0.77V, at

which time LGATE is pulled low. The LGATE pin will continue

to switch high and low at 1.545V and 0.77V until VDD has

gone below the falling POR threshold voltage

VDD_THF.

This provides maximum protection against a shorted

high-side MOSFET while preventing the output voltage from

ringing below ground. The severe-overvoltage fault circuit

can be triggered after another fault has already been

latched.

Gate-Driver Outputs LGATE and UGATE

The ISL6263A has internal high-side and low-side

N-Channel MOSFET gate-drivers. The LGATE driver is

optimized for low duty-cycle applications where the low-side

MOSFET conduction losses are dominant. The LGATE

pull-down resistance is very low in order to clamp the

gate-source voltage of the MOSFET below the V

GS(th)

turnoff. The current transient through the low-side gate at

turnoff can be considerable due to the characteristic large

switching charge of a low r

DS(ON)

MOSFET.

Adaptive shoot-through protection prevents the gate-driver

outputs from going high until the opposite gate-driver output

has fallen below approximately 1V. The UGATE turn-on

propagation delay t

PDRU

and LGATE turn-on propagation

delay t

PDRL

are found in the “Electrical Specifications” table

on page 7. The power for the LGATE gate-driver is sourced

directly from the PVCC pin. The power for the UGATE

gate-driver is sourced from a boot-strap capacitor connected

across the BOOT and PHASE pins. The boot capacitor is

charged from PVCC through an internal boot-strap diode

each time the low-side MOSFET turns on, pulling the

PHASE pin low.

Internal Bootstrap Diode

The ISL6263A has an integrated boot-strap Schottky diode

connected from the PVCC pin to the BOOT pin. Simply

adding an external capacitor across the BOOT and PHASE

pins completes the bootstrap circuit.

The minimum value of the bootstrap capacitor can be

calculated from Equation 3:

where Q

GATE

is the amount of gate charge required to fully

charge the gate of the upper MOSFET. The ΔV

BOOT

term is

defined as the allowable droop in the rail of the upper drive.

As an example, suppose an upper MOSFET has a gate

charge, Q

GATE

, of 25nC at 5V and also assume the droop in

TABLE 3. FAULT PROTECTION SUMMARY OF ISL6263A

FAULT TYPE

FAULT

DURATION

PRIOR TO

PROTECTION

ACTIONS

FAULT

RESET

Overcurrent 120µs LGATE, UGATE, and

PGOOD latched low

Cycle

VR_ON or

VDD

Short Circuit <2µs LGATE, UGATE, and

PGOOD latched low

Cycle

VR_ON or

VDD

Overvoltage

(+195mV)

between VO pin

and SOFT pin

1ms LGATE, UGATE, and

PGOOD latched low

Cycle

VR_ON or

VDD

Severe

Overvoltage

(+1.55V)

between VO pin

and VSS pin

Immediately UGATE, and

PGOOD latched low,

LGATE toggles ON

when VO >1.55V

OFF when

VO <0.77V

until fault reset

Cycle

VDD only

Undervoltage

(-300mV)

between VO pin

and SOFT pin

1ms LGATE, UGATE, and

PGOOD latched low

Cycle

VR_ON or

VDD

PWM

UGATE

PDRL

PDRU

LGATE

FIGURE 6. GATE DRIVER TIMING DIAGRAM

FIGURE 7. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

20nC

ΔV

BOOT_CAP

(V)

BOOT_CAP

(¬µF

2.0

1.6

1.4

1.0

0.8

0.6

0.4

0.2

0.0

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0

GATE

= 100nC

1.2

1.8

BOOT

GATE

ΔV

BOOT

------------------------

≥

(EQ. 3)

ISL6263A

FN9284.3

July 8, 2010

the drive voltage at the end of a PWM cycle is 200mV. One

will find that a bootstrap capacitance of at least 0.125µF is

required. The next larger standard value capacitance is

0.15µF. A good quality ceramic capacitor is recommended.

Soft-Start and Soft Dynamic VID Slew Rates

The output voltage of the converter tracks V

SOFT,

the

voltage across the SOFT and VSS pins. Shown in Figure 1,

the SOFT pin is connected to the output of the VID DAC

through the unidirectional soft-start current source I

or the

bidirectional soft-dynamic VID current source I

DVID

, and the

non-inverting input of the error amplifier. Current is sourced

from the SOFT pin when I

is active. The SOFT pin can

both source and sink current when I

DVID

is active. The

soft-start capacitor C

SOFT

changes voltage at a rate

proportional to I

or I

DVID

. The ISL6263A automatically

selects I

for the soft-start sequence so that the inrush

current through the output capacitors is maintained below

the OCP threshold. Once soft-start has completed, I

DVID

automatically selected for output voltage changes

commanded by the VID inputs, charging C

SOFT

when the

output voltage is commanded to rise, and discharging

SOFT

when the output voltage is commanded to fall.

The IMVP-6+ Render Voltage Regulator specification

requires a minimum of 10mV/µs for SLEWRATE

GFX

. The

value for C

SOFT

must guarantee the minimum slew-rate of

10mV/µs when the soft-dynamic VID current source I

DVID

the minimum specified value in the “Electrical Specifications”

table on page 8. The value of C

SOFT

, can be calculated from

Equation 4:

Choosing the next lower standard component value of

0.015µF will guarantee 10mV/µs SLEWRATE

GFX

. This

choice of C

SOFT

controls the startup slew-rate as well. One

should expect the output voltage during soft-start to slew to

the voltage commanded by the VID settings at a nominal

rate given by Equation 5:

Note that the slewrate is the average rate of change

between the initial and final voltage values.

RBIAS Current Reference

The RBIAS pin is internally connected to a 1.545V reference

through a 3kΩ resistance. A bias current is established by

connecting a ±1% tolerance, 150kΩ resistor between the

RBIAS and VSS pins. This bias current is mirrored, creating the

reference current I

OCSET

that is sourced from the OCSET pin.

Do not connect any other components to this pin, as they will

have a negative impact on the performance of the IC.

Setting the PWM Switching Frequency

The R

modulator scheme is not a fixed-frequency

architecture, lacking a fixed-frequency clock signal to

produce PWM. The switching frequency increases during

the application of a load to improve transient performance.

The static PWM frequency varies slightly depending on the

input voltage, output voltage, and output current, but this

variation is normally less than 10% in continuous conduction

mode.

Refer to Figure 2 and find that resistor R

FSET

is connected

between the V W and COMP pins. A current is sourced from

VW through R

FSET

creating the synthetic ripple window

voltage signal V

which determines the PWM switching

frequency. The relationship between the resistance of R

FSET

and the switching frequency in CCM is approximated by

Equation 6:

For example, the value of R

FSET

for 300kHz operation is

approximately:

This relationship only applies to operation in constant

conduction mode because the PWM frequency naturally

decreases as the load decreases while in diode emulation

mode.

Static Droop Design Using DCR Sensing

The ISL6263A has an internal differential amplifier to

accurately regulate the voltage at the processor die.

For DCR sensing, the process to compensate the DCR

resistance variation takes several iterative steps. Figure 2

shows the DCR sensing method. Figure 8 shows the

simplified model of the droop circuitry. The inductor DC

current generates a DC voltage drop on the inductor DCR.

Equation 8 gives this relationship:

An R-C network senses the voltage across the inductor to

get the inductor current information. R

NTCEQ

represents the

NTC network consisting of R

NTC

, R

NTCS, and

NTCP

. The

choice of R

will be discussed in the following section.

The first step in droop load line compensation is to adjust

NTCEQ

, and R

such that the correct droop voltage

appears even at light loads between the VSUM and VO pins.

As a rule of thumb, the voltage drop V

across the R

NTCEQ

network, is set to be 0.3x to 0.8x V

DCR

. This gain, defined as

, provides a reasonable amount of light load signal from

which to derive the droop voltage.

SOFT

DVIDmin

10mV

μs

----------------

⎝⎠

⎛⎞

-------------------------

180μA

10k

------------------

0.018μF===

(EQ. 4)

SOFT

-----------------------

SOFT

-------------------

42μA

0.015μF

-----------------------

2.8mV

μs

------------------

≈

(EQ. 5)

FSET

T0.510

6–

×–()

400 10

12–

-----------------------------------------

(EQ. 6)

7.1

×10

3.33 10

6–

× 0.5 10

6–

×–()

400 10

12–

--------------------------------------------------------------------

(EQ. 7)

DCR

DCR⋅=

(EQ. 8)

ISL6263A

FN9284.3

July 8, 2010

The NTC network resistor value is dependent on

temperature and is given by Equation 9:

, the gain of V

to V

DCR

, is also dependent on the

temperature of the NTC thermistor shown in Equation 10:

The inductor DCR is a function of temperature and is

approximately given by Equation 11:

The droop amplifier output voltage divided by the total load

current is given by Equation 12:

droop

is the actual load line slope, and 0.00393 is the

temperature coefficient of the copper. To make R

droop

independent of the inductor temperature, it is desired to

have:

where G

1target

is the desired ratio of V

DCR

. Therefore, the

temperature characteristics G

is described by Equation 14:

It is recommended to begin your droop design using the

NTC

, R

NTCS

, and R

NTCP

component values of the

evaluation board available from Intersil.

The gain of the droop amplifier circuit is shown in Equation 15:

After determining R

and R

NTCEQ

networks, use

Equation 16 to calculate the droop resistances R

DRP1

and

DRP2

droop

is 8mΩ per Intel IMVP-6+ specification and R

DRP1

typically 1kΩ.

The effectiveness of the R

NTCEQ

network is sensitive to the

coupling coefficient between the NTC thermistor and the

inductor. The NTC thermistor should be placed in the closet

proximity of the inductor.

To see whether the NTC network successfully compensates

the DCR change over-temperature, one can apply full load

current and wait for the thermal steady state and see how

much the output voltage deviates from the initial voltage

reading. A good compensation can limit the drift to less than

2mV. If the output voltage is decreasing when the temperature

increases, that ratio between the NTC thermistor value and

the rest of the resistor divider network has to be increased.

Following the evaluation board value and layout of NTC

placement will minimize the engineering time.

T()

NTC

NTCS

+()R

NTCP

⋅

NTC

NTCS

NTCP

------------------------------------------------------------------------

(EQ. 9)

T()

T() R

-------------------------------

(EQ. 10)

DCR T() DCR

25°C

1 0.00393 T 25°C–()⋅+()⋅=

(EQ. 11)

droop

T()DCR

25°C

1 0.00393 T 25°C–()⋅+()k

droopamp

⋅⋅ ⋅=

(EQ. 12)

T() 1 0.00393 T 25°C–()⋅+()⋅ G

1t etarg

≅

(EQ. 13)

T()

1t etarg

1 0.00393 T 25°C–()⋅+()

---------------------------------------------------------------------

(EQ. 14)

droopamp

DRP2

DRP1

-------------------

(EQ. 15)

DRP2

droop

DCR G

125°C()

⋅

-------------------------------------------

⎝⎠

⎜⎟

⎛⎞

1–

⎝⎠

⎜⎟

⎛⎞

DRP1

⋅=

(EQ. 16)

FIGURE 8. EQUIVALENT MODEL FOR DROOP CIRCUIT USING INDUCTOR DCR CURRENT SENSING

VSUM

DFB

−

OCP

OCSET

DROOP

OCSET

DRP1

DRP2

VDD

10µA

NTCEQ

DCR

ISL6263A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

ISL6263AIRZ

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Manufacturer:

Renesas / Intersil

Description:

Switching Voltage Regulators ONE-PHS INT DC/DC BUCK CNTRLR IMVP-6

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