RT8009
10
DS8009-07 March 2011www.richtek.com
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used
by the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability problem.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8009.
` For the main current paths as indicated in bold lines in
Figure 6 keep their traces short and wide.
` Put the input capacitor as close as possible to the device
pins (VIN and GND).
` LX node is with high frequency voltage swing and should
be kept small area. Keep analog components away from
LX node to prevent stray capacitive noise pick-up.
curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
P
D(MAX)
= ( T
J(MAX)
- T
A
) / θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature 125°C, T
A
is the ambient temperature and the
θ
JA
is the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8009 DC/DC converter, where T
J (MAX)
is the maximum
junction temperature of the die (125°C) and T
A
is the
maximum ambient temperature. The junction to ambient
thermal resistance θ
JA
is layout dependent. For
SOT-23-5/TSOT-23-5 packages, the thermal resistance θ
JA
is 250°C/W on the standard JEDEC 51-3 single-layer
thermal test board. The maximum power dissipation at
T
A
= 25°C can be calculated by following formula :
P
D(MAX)
= ( 125°C - 25°C ) / 250 = 0.4 W for SOT-23-5/
TSOT-23-5 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
. For RT8009 packages, the Figure 5 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
The value of junction to case thermal resistance θ
JC
is
popular for users. This thermal parameter is convenient
for users to estimate the internal junction operated
temperature of packages while IC operating. It's
independent of PCB layout, the surroundings airflow effects
and temperature difference between junction to ambient.
The operated junction temperature can be calculated by
following formula :
T
J
= T
C
+ P
D
x θ
JC
Where T
C
is the package case (Pin 2 of package leads)
temperature measured by thermal sensor, P
D
is the power
dissipation defined by user's function and the θ
JC
is the
junction to case thermal resistance provided by IC
manufacturer. Therefore it's easy to estimate the junction
temperature by any condition.
Figure 5. Derating Curves for RT8009 Package
0
50
100
150
200
250
300
350
400
450
0 20 40 60 80 100 120 140
Ambient Temperature (°C)
Maximum Power Dissipation (mW)
Single Layer PCB
SOT-23-5, TSOT-23-5 Packages
