NCP1200A
http://onsemi.com
13
A simple and inexpensive solution helps circumventing both problems, negative biasing, and gate high transient. It consists
in a solution using one 1N4007 (or two in a series for safety) forcing the V
CC
capacitor to deplete at the same rate as the bulk
capacitor does. Figure 24 shows the solution.
Figure 24. A Diode Forces the V
CC
Capacitor to
Quickly Discharge at Poweroff
CV
CC
8
7
6
5
1
2
3
4
+
Cbulk
+
3
1N4007
NCP1200A
or
1N4007
1N4007
When the bulk naturally depletes at poweroff, the diode brings the V
CC
down as soon as Vbulk drops below V
CC
. This
ensures a clean turnoff and the above problems go away.
V
CC
VFB
Vbulk
Vgs
Figure 25. The Diode Addition Forces a Clean Turnoff Sequence both Negative Biasing
and Gate High State Troubles
Once implemented, please make sure that your operating waveforms match those of Figure 25. That is to say, a bulk level
depleting the V
CC
capacitor at turnoff. To summarize:
1. Wire a diode between V
CC
and the bulk capacitor as illustrated by Figure 24.
2. Select a MOSFET affected by a standard V
T
, minimum of 2 V, maximum of 4 V.
3. Check that final waveforms match Figure 25 signals
NCP1200A
http://onsemi.com
14
ORDERING INFORMATION
Device Type Marking Package Shipping
NCP1200AP40 1200AP40 PDIP8 50 Units / Rail
NCP1200AP40G
F
SW
= 40 kHz
1200AP40 PDIP8
(PbFree)
50 Units / Rail
NCP1200AD40R2 200A4 SOIC8 2500 Units /Reel
NCP1200AP60 1200AP60 PDIP8 50 Units / Rail
NCP1200AP60G
F 60 kHz
1200AP60 PDIP8
(PbFree)
50 Units / Rail
NCP1200AD60R2
F
SW
= 60 kHz
200A6 SOIC8 2500 Units /Reel
NCP1200AD60R2G 200A6 SOIC8
(PbFree)
2500 Units /Reel
NCP1200AP100 1200AP100 PDIP8 50 Units / Rail
NCP1200AP100G
F 100 kHz
1200AP100 PDIP8
(PbFree)
50 Units / Rail
NCP1200AD100R2
F
SW
= 100 kHz
200A1 SOIC8 2500 Units / Reel
NCP1200AD100R2G 200A1 SOIC8
(PbFree)
2500 Units / Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP1200A
http://onsemi.com
15
PACKAGE DIMENSIONS
SOIC8
D SUFFIX
CASE 75107
ISSUE AD
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒ
mm
inches
Ǔ
SCALE 6:1
SEATING
PLANE
1
4
58
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW
STANDARD IS 75107.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010) Z
S
X
S
M
____

NCP1200AD60R2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC CTRLR PWM CM HV 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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