NCP1200A
http://onsemi.com
7
APPLICATION INFORMATION
Introduction
The NCP1200A implements a standard current mode
architecture where the switchoff time is dictated by the
peak current setpoint. This component represents the ideal
candidate where low partcount is the key parameter,
particularly in lowcost ACDC adapters, auxiliary
supplies, etc. Due to its highperformance HighVoltage
technology, the NCP1200A incorporates all the necessary
components normally needed in UC384X based supplies:
timing components, feedback devices, lowpass filter and
selfsupply. This later point emphasizes the fact that
ON Semiconductors NCP1200A does NOT need an
auxiliary winding to operate: the product is naturally
supplied from the highvoltage rail and delivers a V
CC
to the
IC. This system is called the Dynamic SelfSupply (DSS).
Dynamic SelfSupply
The DSS principle is based on the charge/discharge of the
V
CC
bulk capacitor from a low level up to a higher level. We
can easily describe the current source operation with a bunch
of simple logical equations:
POWERON: IF V
CC
< VCC
H
THEN Current Source is
ON, no output pulses
IF V
CC
decreasing > VCC
L
THEN Current Source is OFF,
output is pulsing
IF V
CC
increasing < VCC
H
THEN Current Source is ON,
output is pulsing
Typical values are: VCC
H
= 12 V, VCC
L
= 10 V
To better understand the operational principle, Figure 15’s
sketch offers the necessary light:
Figure 15. The charge/discharge cycle over a
10 mF V
CC
capacitor
10.0 M 30.0 M 50.0 M 70.0 M 90.0 M
V
CC
Current
Source
OFF
ON
OUTPUT PULSES
V
ripple
= 2 V
UVLO
H
= 12 V
UVLO
L
= 10 V
The DSS behavior actually depends on the internal IC
consumption and the MOSFETs gate charge Qg. If we select
a MOSFET like the MTP2N60E, Qg max equals 22 nC.
With a maximum switching frequency of 68 kHz for the P60
version, the average power necessary to drive the MOSFET
(excluding the driver efficiency and neglecting various
voltage drops) is:
F
SW
Qg V
CC
with
F
SW
= maximum switching frequency
Qg = MOSFETs gate charge
V
CC
= V
GS
level applied to the gate
To obtain the final IC current, simply divide this result by
V
CC
: I
driver
= F
SW
Qg = 1.5 mA. The total standby power
consumption at noload will therefore heavily rely on the
internal IC consumption plus the above driving current
(altered by the drivers efficiency). Suppose that the IC is
supplied from a 350 VDC line. The current flowing through
pin 8 is a direct image of the NCP1200A consumption
(neglecting the switching losses of the HV current source).
If ICC2 equals 2.3 mA @ T
J
= 25°C, then the power
dissipated (lost) by the IC is simply: 350 x 2.3 m = 805 mW.
For design and reliability reasons, it would be interesting to
reduce this source of wasted power which increases the die
temperature. This can be achieved by using different
methods:
1. Use a MOSFET with lower gate charge Qg
2. Connect pin through a diode (1N4007 typically) to
one of the mains input. The average value on pin 8
becomes
V
MAINS(peak) @ 2
p
. Our power
contribution example drops to: 223 x 2.3 m = 512
mW. If a resistor is installed between the mains and
the diode, you further force the dissipation to
migrate from the package to the resistor. The
resistor value should account for lowline startup.
3. Permanently force the V
CC
level above VCC
H
with
an auxiliary winding. It will automatically
disconnect the internal startup source and the IC
will be fully selfsupplied from this winding.
Again, the total power drawn from the mains will
significantly decrease. Make sure the auxiliary
voltage never exceeds the 16 V limit.
NCP1200A
http://onsemi.com
8
Figure 16. A simple diode naturally reduces the average voltage on pin 8
8
7
6
5
1
2
3
4
mains
Cbulk
HV
Skipping Cycle Mode
The NCP1200A automatically skips switching cycles
when the output power demand drops below a given level.
This is accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the socalled skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 18).
Suppose we have the following component values:
Lp, primary inductance = 1 mH
F
SW
, switching frequency = 61 kHz
Ip skip = 200 mA (or 333 mV/R
SENSE
)
The theoretical power transfer is therefore:
1
2
@ Lp @ Ip
2
@ F
SW
+ 1.2 W
If this IC enters skip cycle mode with a bunch length of
20 ms over a recurrent period of 100 ms, then the total
power transfer is: 1.2 . 0.2 = 240 mW.
To better understand how this skip cycle mode takes place,
a look at the operation mode versus the FB level
immediately gives the necessary insight:
Figure 17.
SKIP CYCLE OPERATION
I
P(min)
= 333 mV/R
SENSE
NORMAL CURRENT
MODE OPERATION
FB
1 V
4.2 V, FB Pin Open
3.2 V, Upper
Dynamic Range
When FB is above the skip cycle threshold (1 V by
default), the peak current cannot exceed 1 V/R
SENSE
. When
the IC enters the skip cycle mode, the peak current cannot go
below Vpin1 / 3.3. The user still has the flexibility to alter
this 1 V by either shunting pin 1 to ground through a resistor
or raising it through a resistor up to the desired level.
Grounding pin 1 permanently invalidates the skip cycle
operation.
Power P1
Power P2
Power P3
Figure 18. Output Pulses at Various Power Levels (X = 5.0 ms/div) P1 t P2 t P3
NCP1200A
http://onsemi.com
9
Figure 19. The Skip Cycle Takes Place at Low Peak Currents which Guaranties NoiseFree
Operation
315.40 882.70 1.450 M 2.017 M 2.585 M
300 M
200 M
100 M
0
MAX PEAK
CURRENT
SKIP CYCLE
CURRENT LIMIT
We recommend a pin 1 operation between 400 mV and 1.3
V that will fix the skip peak current level between 120 mV
/ RSENSE and 390 mV / RSENSE.
NonLatching Shutdown
In some cases, it might be desirable to shut off the part
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
and ground. By pulling FB below the Adj pin 1 level, the
output pulses are disabled as long as FB is pulled below
pin 1. As soon as FB is relaxed, the IC resumes its operation.
Figure 20 depicts the application example:
Figure 20. Another Way of Shutting Down the IC without a Definitive Latchoff State
ON/OFF
Q1
8
7
6
5
1
2
3
4

NCP1200AD60R2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC CTRLR PWM CM HV 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union