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MAX113CAG

P1-P3P4-P6P7-P9P10-P12
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
DD
= +3V, T
A
= +25°C, unless otherwise noted.) (Note 4)
Note 4: Input control signals are specified with t
r
= t
f
= 5ns, 10% to 90% of 3V, and timed from a voltage level of 1.3V. Timing
delays get shorter at higher supply voltages. See the Conversion Time vs. Supply Voltage graph in the
Typical Operating
Characteristics
to extrapolate timing delays at other power-supply voltages.
Note 5: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.66V or 2.0V.
Note 6: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V.
Note 7: Also defined as the Minimum Address-Valid to Convert-Start Time.
0.8 100.66 10
WR Pulse Width
t
WR
0.6 10 µs
700
Minimum
Acquisition Time
t
ACQ
450 ns(Note 7) 600
MAX117M
MIN MAXMIN TYP MAX
PARAMETER SYMBOL
MIN MAX
UNITSCONDITIONS MAX117C/E
T
A
= +25°C
ALL GRADES
T
A
= T
MIN
to T
MAX
250
Data Access Time
(WR-RD Mode)
t
ACC2
180 ns
t
RD
> t
INTL
, C
L
= 100pF
(Note 5)
220
1.0
600
150
600
400
1.8
70
250
240
Data Access Time
After INT
t
ID
Delay Between WR
and RD Pulses
t
RD
0.8 µs
RD Pulse Width
(WR-RD Mode)
t
READ1
400 ns
100 ns
Multiplexer Address
Hold Time
Data Access Time
(WR-RD Mode)
t
ACC1
400 ns
RD to INT Delay
t
RI
300 ns
WR to INT Delay
t
INTL
0.7 1.45 µs
t
AH
50 ns
Pipelined mode, C
L
= 100pF
RD Pulse Width
(WR-RD Mode)
t
READ2
180 ns
WR to INT Delay
t
IHWR
180 ns
0.9
500
130
t
RD
> t
INTL
, determined by
t
ACC2
t
RD
< t
INTL
, determined by
t
ACC1
500
t
RD
< t
INTL
, C
L
= 100pF
(Note 5)
340
C
L
= 50pF
Pipelined mode, C
L
= 50pF
1.6
60
220
200
150
0
0
140
t
CRD
+
150
180
130
0
0
120
t
CRD
+
130
170
Data Hold Time t
DH
100 ns
CS to RD, WR
Setup Time
t
CSS
0 ns
CS to RD, WR
Hold Time
t
CSH
0 ns
CS to RDY Delay
t
RDY
100 ns
(Note 6)
Data Access Time
(RD Mode)
t
ACC0
t
CRD
+
100
ns
RD to INT Delay
(RD Mode)
t
INTH
100 160 ns
C
L
= 100pF (Note 5)
C
L
= 50pF,
R
L
= 5.1kΩ to V
DD
C
L
= 50pF
2.42.06
Conversion Time
(WR-RD Mode)
t
CWR
1.8 µs
t
RD
< t
INTL
, C
L
= 100pF
(Note 5)
1.41.2
Power-Up Time t
UP
0.9 µs
2.62.4
Conversion Time
(RD Mode)
t
CRD
2.0 µs
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
_______________________________________________________________________________________
5
1.6
0.4
-60 140
CONVERSION TIME
vs. AMBIENT TEMPERATURE
0.6
1.4
TEMPERATURE (°C)
t
CRD
(NORMALIZED TO VALUE
AT V
DD
= +3.3V, +25°C)
60
1.0
0.8
-20 20 100
1.2
V
DD
= 3.3V
V
DD
= 3.6V
V
DD
= 3.0V
MAX113/117-01
8.0
4.0
1k 10k 100k
EFFECTIVE BITS vs. 
INPUT FREQUENCY (WR-RD MODE)
INPUT FREQUENCY (Hz)
EFFECTIVE BITS
1M
7.5
7.0
6.5
6.0
5.5
5.0
4.5
f
SAMPLE
= 400kHz
V
IN
= 2.98Vp-p
MAX113/117-02
-100
0 200
SIGNAL-TO-NOISE RATIO
FREQUENCY (kHz)
SNR (dB)
120
-80
40 80 160
-40
0
-20
-60
MAX113/117-03
f
IN
= 30.27kHz
V
IN
= 2.88Vp-p
f
SAMPLE
= 400ksps
SNR = 48.8dB
1400
800
2.8 4.0
CONVERSION TIME
vs. SUPPLY VOLTAGE
900
1300
SUPPLY VOLTAGE (V)
t
CRD
(ns)
3.6
1100
1000
3.0 3.4 3.8
1200
3.2
MAX113/117-04
4
5
0
1
AVERAGE POWER CONSUMPTION
vs. SAMPLING RATE USING PWRDN
1
3
SAMPLING RATE (ksps)
POWER DISSIPATION (mW)
1000
2
10 100
MAX113/117-06
5
0
120 160 240 320
TOTAL UNADJUSTED ERROR
vs. POWER-UP TIME
1
4
MAX113/117-08
t
UP
(ns)
TUE (LSB)
200 280
3
2
V
DD
= 3.0V
V
DD
= 3.6V
__________________________________________Typical Operating Characteristics
(V
DD
= +3V, T
A
= +25°C, unless otherwise noted.)
V
DD
= 5.25V
4
0
-60 140
SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDING REFERENCE CURRENT)
1
2
3
MAX113/117-10
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
60 100-20 20
V
DD
= 3.3V
V
DD
= 3.0V
MAX113/MAX117
+3V, 400ksps, 4/8-Channel,
8-Bit ADCs with 1µA Power-Down
6 _______________________________________________________________________________________
______________________________________________________________Pin Description
Mode Selection Input. Internally pulled low with a 15µA current source. MODE = 0
activates read mode; MODE = 1 activates write-read mode (see
Digital Interface
section).
MODE5
Analog Input Channel 6IN6—
FUNCTION
Three-State Data Outputs D1, D2, D37, 8, 9
Three-State Data Output (LSB)D06
Lower limit of reference span. REF- sets the zero-code voltage. Range is GND ≤
V
REF-
< V
REF+
.
REF-13
GroundGND12
Interrupt Output. INT goes low to indicate end of conversion (see
Digital Interface
section).
INT
11
Read Input. RD must be low to access data (see
Digital Interface
section).RD
10
Write-Control Input/Ready-Status Output (see
Digital Interface
section)
WR/RDY
15
Upper limit of reference span. REF+ sets the full-scale input voltage. Range is
V
REF-
< V
REF+
≤ V
DD
. Internally hardwired to IN8 (Table 1).
REF+14
Multiplexer Channel Address Input (MSB)A2—
Three-State Data Output (MSB)D720
Positive Supply, +3.0V to +3.6VV
DD
24
Power-Down Input. PWRDN reduces supply current when low.PWRDN
23
Multiplexer Channel Address Input (LSB)A022
Multiplexer Channel Address Input A121
Analog Input Channel 7IN7—
Three-State Data Outputs D4, D5, D617, 18, 19
Chip-Select Input. CS must be low for the device to recognize WR or RD inputs.CS
16
9, 10, 11
8
15
14
13
12
17
16
23
22
27
PIN
7
1
26
25
24
28
19, 20, 21
18
MAX113
NAME
MAX117
Analog Input Channel 5IN5— 2
Analog Input Channel 1
Analog Input Channel 2IN23
IN1
5
4 6
Analog Input Channel 3
Analog Input Channel 4IN41
IN3
3
2 4
P1-P3P4-P6P7-P9P10-P12

MAX113CAG

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IC ADC 4CH8BIT 3V 100KSPS 24SSOP
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