MAX1177BCUP+ Datasheet MAX1177ACUP+, MAX1177AEUP+, MAX1177BCUP+ | P7-P9

Detailed Description

Converter Operation

The MAX1177 uses a successive-approximation (SAR)

conversion technique with an inherent track-and-hold

(T/H) stage to convert an analog input into a 16-bit digital

output. Parallel outputs provide a high-speed interface to

microprocessors (µPs). The Functional Diagram shows a

simplified internal architecture of the MAX1177. Figure 3

shows a typical operating circuit for the MAX1177.

Analog Input

Input Scaler

The MAX1177 has an input scaler, which allows conver-

sion of input voltages ranging from 0 to 10V, while oper-

ating from a single +5V analog supply. The input scaler

attenuates and shifts the analog input to match the input

range of the internal digital-to-analog converter (DAC).

Figure 4 shows the equivalent input circuit of the

MAX1177. This circuit limits the current going into AIN to

less than 2mA.

Track and Hold (T/H)

In track mode, the internal hold capacitor acquires the

analog signal (Figure 4). In hold mode, the T/H switches

open and the capacitive DAC samples the analog input.

During the acquisition, the analog input (AIN) charges

capacitor C

HOLD

. The acquisition ends on the second

falling edge of CS. At this instant, the T/H switches

open. The retained charge on C

HOLD

represents a sam-

ple of the input. In hold mode, the capacitive DAC

adjusts during the remainder of the conversion time to

restore node T/H OUT to zero within the limits of 16-bit

resolution. Force CS low to put valid data on the bus

after conversion is complete.

MAX1177

16-Bit, 135ksps, Single-Supply ADC

with 0 to 10V Input Range

_______________________________________________________________________________________ 7

DGND

1mA

LOAD

= 20pF

DO–D15

LOAD

= 20pF

1mA

DGND

a) HIGH-Z TO V

TO V

, AND

TO HIGH-Z

b) HIGH-Z TO V

TO V

, AND

TO HIGH-Z

Figure 1. Load Circuits

R/C

REF POWER-

DOWN CONTROL

EOC

ACQ

CONV

CSH

CSL

EOC

HBEN

D7/D15–D0/D8

HIGH/LOW

BYTE VALID

HIGH/LOW

BYTE VALID

DO1

HIGH-Z

Figure 2. MAX1177 Timing Diagram

MAX1177

Power-Down Modes

Select standby mode or shutdown mode with the R/C

bit during the second falling edge of CS (see the

Selecting Standby or Shutdown Mode section). The

MAX1177 automatically enters either standby mode

(reference and buffer on) or shutdown (reference and

buffer off) after each conversion, depending on the sta-

tus of R/C during the second falling edge of CS.

Internal Clock

The MAX1177 generates an internal conversion clock to

free the µP from the burden of running the SAR conver-

sion clock. Total conversion time (t

CONV

) after entering

hold mode (second falling edge of CS) to end-of-con-

version (EOC) falling is 4.7µs (max).

Applications Information

Starting a Conversion

CS and R/C control acquisition and conversion in the

MAX1177 (Figure 2). The first falling edge of CS powers

up the device and puts it in acquire mode if R/C is low.

The convert start is ignored if R/C is high. The device

needs at least 12ms for the internal reference to wake

up and settle before starting the conversion (C

REFADJ

= 0.1µF, C

REF

= 10µF), if powering up from shutdown.

Selecting Standby or Shutdown Mode

The MAX1177 has a selectable standby or low-power

shutdown mode. In standby mode, the ADC’s internal

reference and reference buffer do not power down

between conversions, eliminating the need to wait for

the reference to power up before performing the next

conversion. Shutdown mode powers down the refer-

ence and reference buffer after completing a conver-

sion. The reference and reference buffer require a

minimum of 12ms to power up and settle from shut-

down (C

REFADJ

= 0.1µF, C

REF

= 10µF).

The state of R/C at the second falling edge of CS

selects which power-down mode the MAX1177 enters

upon conversion completion. Holding R/C low causes

the device to enter standby mode. The reference and

buffer are left on after the conversion completes. R/C

high causes the MAX1177 to enter shutdown mode and

power-down the reference and buffer after conversion

(Figures 5 and 6). Set the voltage at R/C high during

the second falling edge of CS to realize the lowest cur-

rent operation.

16-Bit, 135ksps, Single-Supply ADC

with to 10V Input Range

8 _______________________________________________________________________________________

S1, S2 = T/H SWITCH

R2 = 3.92kΩ

R3 = 17.79kΩ

AIN

3.4kΩ

17.79kΩ

3.92kΩ

T/H OUT

HOLD

TRACK

HOLD

30pF

161Ω

MAX1177

Figure 4. Equivalent Input Circuit

D0–D7

D8–D15

µP DATA

BUS

AGND DGND

+5V ANALOG +5V DIGITAL

ANALOG INPUT AIN

HBEN

EOC

R/C

REF

REFADJ

HIGH

BYTE

LOW

BYTE

10µF

0.1µF

MAX1177

Figure 3. Typical Operating Circuit for the MAX1177

Standby Mode

While in standby mode, the supply current is less than

3.7mA (typ). The next falling edge of CS with R/C low

causes the MAX1177 to exit standby mode and begin

acquisition. The reference and reference buffer remain

active to allow quick turn-on time.

Shutdown Mode

In shutdown mode, the reference and reference buffer

are shut down between conversions. Shutdown mode

reduces supply current to 0.5µA (typ) immediately after

the conversion. The next falling edge of CS with R/C

low causes the reference and buffer to wake up and

enter acquisition mode. To achieve 16-bit accuracy,

allow 12ms for the internal reference to wake up

REFADJ

= 0.1µF, C

REF

= 10µF).

Internal and External Reference

Internal Reference

The internal reference of the MAX1177 is internally

buffered to provide +4.096V output at REF. Bypass

REF to AGND and REFADJ to AGND with 10µF and

0.1µF, respectively. Sink or source current at REFADJ

to make fine adjustments to the internal reference. The

input impedance of REFADJ is nominally 5kΩ. Use the

circuit in Figure 7 to adjust the internal reference to

±1.5%.

External Reference

An external reference can be placed at either the input

(REFADJ) or the output (REF) of the MAX1177’s internal

buffer amplifier. Using the buffered REFADJ input

makes buffering the external reference unnecessary.

The input impedance of REFADJ is typically 5kΩ. The

internal buffer output must be bypassed at REF with a

10µF capacitor.

Connect REFADJ to AV

to disable the internal buffer.

Directly drive REF using an external 3.8V to 4.2V refer-

ence. During conversion, the external reference must

be able to drive 100µA of DC load current and have an

output impedance of 10Ω or less.

For optimal performance, buffer the reference through

an op amp and bypass REF with a 10µF capacitor.

Consider the MAX1177’s equivalent input noise (0.6

LSB) when choosing a reference.

MAX1177

16-Bit, 135ksps, Single-Supply ADC

with 0 to 10V Input Range

_______________________________________________________________________________________ 9

R/C

EOC

REF AND

BUFFER

POWER

ACQUISITION CONVERSION

DATA

OUT

Figure 5. Selecting Standby Mode

R/C

EOC

REF AND

BUFFER

POWER

ACQUISITION CONVERSION

DATA

OUT

Figure 6. Selecting Shutdown Mode

+5V

68kΩ

100kΩ

150kΩ

0.1µF

REFADJ

MAX1177

Figure 7. MAX1177 Reference Adjust Circuit

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

MAX1177BCUP+

Mfr. #:

Buy MAX1177BCUP+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 16-Bit, 135ksps, Single-Supply ADC with 0 to 10V Input Range

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MAX1177BCUP+

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