MAX7319ATE+T Datasheet MAX7319ATE+T, MAX7319AEE+, MAX7319ATE+ | P7-P9

of the I

C specification. Therefore, address inputs AD2

and AD0 that are connected to SDA or SCL normally

appear at power-up to be connected to V+. The pullup

selection logic uses AD0 to select whether pullups are

enabled for ports I3–I0, and uses AD2 to select whether

pullups are enabled for ports I7–I4. The rule is that a

logic-high SDA or SCL connection selects the pullups,

while a logic-low deselects the pullups (Table 3). The

pullup configuration is correct on power-up for a stan-

dard I

C configuration, where SDA and SCL are pulled

up to V+ by the external I

C pullup resistors.

There are circumstances where the assumption that

SDA = SCL = V+ on power-up is not true, for example,

in true hot-swap applications, in which there is legiti-

mate bus activity during power-up. Also, if SDA and

SCL are terminated with pullup resistors to a different

supply voltage than the MAX7319’s supply voltage, and

if that pullup supply rises later than the MAX7319’s sup-

ply, then SDA or SCL may appear at power-up to be

connected to GND. In such applications, use the four

address combinations that are selected by connecting

address inputs AD2 and AD0 to V+ or GND (shown in

bold in Table 3). These selections are guaranteed to be

correct at power-up, independent of SDA and SCL

behavior. If one of the other 12 address combinations is

used, be aware that an unexpected combination of

pullups might be asserted until the first I

C transmis-

sion (to any device, not necessarily the MAX7319) is

put on the bus.

Port Inputs

Port inputs switch at CMOS logic levels as determined

by the expander’s supply voltage, and are overvoltage

tolerant to +6V, independent of the expander’s supply

voltage.

Port-Input Transition Detection

All eight input ports are monitored for changes since

the expander was last accessed through the serial

interface. The state of the input ports is stored in an

internal “snapshot” register for transition monitoring.

The snapshot is continuously compared with the actual

input conditions, and if a change is detected for any

port input, an internal transition flag is set for that port.

The eight port inputs are sampled (internally latched

into the snapshot register) and the old transition flags

cleared during the I

C acknowledge of every MAX7319

read and write access. The previous port transition

flags are read through the serial interface as the sec-

ond byte of a 2-byte read sequence.

MAX7319

C Port Expander with Eight Inputs and

Maskable Transition Detection

_______________________________________________________________________________________ 7

PART

C SLAVE

ADDRESS

INPUTS

INTERRUPT

MASK

OPEN-

DRAIN

OUTPUTS

PUSH-

PULL

OUTPUTS

C DATA WRITE I

C DATA READ

MAX7319 110xxxx 8 Yes — —

<I7–I0 interrupt

mask>

<I7–I0 port inputs>

<I7–I0 transition flags>

MAX7320 101xxxx — — — 8

<O7–O0 port

outputs>

<O7–O0 port inputs>

MAX7321 110xxxx Up to 8 — Up to 8 —

<P7–P0 port

outputs>

<P7–P0 port inputs>

<P7–P0 transition flags>

MAX7322 110xxxx 4 Yes — 4

<O7, O6 outputs,

I5–I2 interrupt

mask, O1, O0

outputs>

<O7, O6, I5–I2, O1, O0 port

inputs>

<0, 0, I5–I2 transition flags,

0, 0>

MAX7323 110xxxx Up to 4 — Up to 4 4 <port outputs>

<O7, O6, P5–P2, O1, O0 port

inputs>

<0, 0, P5–P2 transition flags,

0, 0>

MAX7328 0100xxx Up to 8 — Up to 8 —

<P7–P0 port

outputs>

<P7–P0 port inputs>

MAX7329 0111xxx Up to 8 — Up to 8 —

<P7–P0 port

outputs>

<P7–P0 port inputs>

Table 2. Read and Write Access to Eight-Port Expander Family

MAX7319

A long read sequence (more than 2 bytes) can be used

to poll the expander continuously without the overhead

of resending the slave address. If more than 2 bytes

are read from the expander, the expander repeatedly

returns the input port data followed by the transition

flags. The inputs are repeatedly resampled and the

transition flags repeatedly reset for each pair of bytes

read. All changes that occur during a long read sequence

are detected and reported.

The MAX7319 includes an 8-bit interrupt mask register

that selects which inputs generate an interrupt upon

change. Each input’s transition flag is set when its input

changes, independent of the interrupt mask register

settings. The interrupt mask register allows the proces-

sor to be interrupted for critical events, while the inputs

and the transition flags can be polled periodically to

detect less critical events.

The INT logic ensures that unnecessary interrupts are

not asserted, yet data transitions are detected and

reported regardless of when the transition occurs. The

INT output is not reasserted during a read sequence to

avoid recursive reentry into an interrupt service routine.

If transition occurs during read sequence, the INT

assertion is delayed until the STOP condition, however,

INT is not reasserted upon a STOP condition if the

changed input data is read before the STOP occurs.

Transition-Detection Masks

The transition-detection logic incorporates a transition

flag and an interrupt mask bit for each input port. The

eight change flags can be read through the serial inter-

face, and the 8-bit interrupt mask is set through the ser-

ial interface.

Each port’s transition flag is set when that port’s input

changes, and the transition flag remains set even if the

input returns to its original state. The port’s interrupt

mask determines whether a transition on that input port

generates an interrupt. Enable interrupts for high-priori-

ty inputs using the interrupt mask. The interrupt allows

the system to respond quickly to changes on these

inputs. Poll the MAX7319 periodically to monitor less-

important inputs. The transition flags indicate whether a

permanent or transient change has occurred on any

input since the MAX7319 was last accessed.

Serial Interface

Serial Addressing

The MAX7319 operates as a slave that sends and

receives data through an I

C interface. The interface

uses a serial data line (SDA) and a serial clock line (SCL)

to achieve bidirectional communication between mas-

ter(s) and slave(s). The master initiates all data transfers

to and from the MAX7319 and generates the SCL clock

that synchronizes the data transfer (Figure 1).

C Port Expander with Eight Inputs and

Maskable Transition Detection

8 _______________________________________________________________________________________

PIN CONNECTION DEVICE ADDRESS 40kΩ INPUT PULLUP ENABLED

AD2 AD0 A6 A5 A4 A3 A2 A1 A0 I7 I6 I5 I4 I3 I2 I1 I0

SCL GND 1100000YYYY————

SCL V+ 1100001YYYYYYYY

SCL SCL 1 1 0 0 0 1 0 Y Y Y Y Y Y Y Y

SCL SDA 1 1 0 0 0 1 1 Y Y Y Y Y Y Y Y

SDA GND 1100100YYYY————

SDA V+ 1100101YYYYYYYY

SDA SCL 1 1 0 0 1 1 0 Y Y Y Y Y Y Y Y

SDA SDA 1 1 0 0 1 1 1 Y Y Y Y Y Y Y Y

GND GND 1 1 0 1 0 0 0 — — — — — — — —

GND V+ 1101001————YYYY

GND SCL 1101010————YYYY

GND SDA 1101011————YYYY

V+ GND 1101100YYYY————

V+ V+ 1101101YYYYYYYY

V+ SCL 1101110YYYYYYYY

V+ SDA 1101111YYYYYYYY

Table 3. MAX7319 Address Map

SDA operates as both an input and an open-drain out-

put. A pullup resistor, typically 4.7kΩ, is required on

SDA. SCL operates only as an input. A pullup resistor,

typically 4.7kΩ, is required on SCL if there are multiple

masters on the 2-wire interface, or if the master in a sin-

gle-master system has an open-drain SCL output.

Each transmission consists of a START condition sent

by a master, followed by the MAX7319’s 7-bit slave

address plus R/W bit, then 1 or more data bytes, and

finally a STOP condition (Figure 2).

START and STOP Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, the master

issues a STOP (P) condition by transitioning SDA from

low to high while SCL is high. The bus is then free for

another transmission (Figure 2).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 3).

Acknowledge

The acknowledge bit is a clocked 9th bit the recipient

uses to acknowledge receipt of each byte of data

(Figure 4). Each byte transferred effectively requires 9

bits. The master generates the 9th clock pulse, and the

recipient pulls down SDA during the acknowledge

clock pulse, so the SDA line is stable low during the

high period of the clock pulse. When the master is

transmitting to the MAX7319, the MAX7319 generates

the acknowledge bit because the device is the recipient.

When the MAX7319 is transmitting to the master, the

master generates the acknowledge bit because the

master is the recipient.

MAX7319

C Port Expander with Eight Inputs and

Maskable Transition Detection

_______________________________________________________________________________________ 9

SCL

SDA

BUF

START

CONDITION

STOP

CONDITION

REPEATED START CONDITION

START CONDITION

SU,STO

HD,STA

SU,STA

HD,DAT

SU,DAT

LOW

HIGH

HD,STA

Figure 1. 2-Wire Serial-Interface Timing Details

SDA

SCL

START

CONDITION

STOP

CONDITION

Figure 2. START and STOP Conditions

SDA

SCL

DATA LINE STABLE;

DATA VALID

CHANGE OF DATA

ALLOWED

Figure 3. Bit Transfer

SCL

SDA BY

TRANSMITTER

CLOCK PULSE

FOR ACKNOWLEDGMENT

START

CONDITION

SDA BY

RECEIVER

12 89

Figure 4. Acknowledge

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

MAX7319ATE+T

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