10
FN9057.6
September 15, 2015
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage V
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6439) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The expressions in Equation 5 relate the
compensation network’s poles, zeros and gain to the
components (R
1
, R
2
, R
3
, C
1
, C
2
, and C
3
) in Figure 5. Use
these guidelines for locating the poles and zeros of the
compensation network:
1. Pick gain (R
2
/R
1
) for desired converter bandwidth.
2. Place first zero below filter’s double pole (~75% F
LC
).
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin - repeat if necessary.
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
P2
with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Charge Pump Capacitor Selection
A capacitor across pins CT1 and CT2 is required to create
the proper bias voltage for the ISL6439 when operating the
IC from 3.3V. Selecting the proper capacitance value is
important so that the bias current draw and the current
required by the MOSFET gates do not overburden the
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R
1
R
3
R
2
C
3
C
1
C
2
COMP
V
OUT
FB
Z
FB
ISL6439
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
OSC
F
LC
1
2 x L
O
x C
O
------------------------------------------
=
F
ESR
1
2 x ESR x C
O
-------------------------------------------
=
(EQ. 4)
F
Z2
1
2 x R
1
R
3
+ x C
3
-------------------------------------------------------
=
F
P1
1
2 x R
2
x
C
1
x C
2
C
1
C
2
+
----------------------



---------------------------------------------------------
=
F
P2
1
2 x R
3
x C
3
------------------------------------
=
F
Z1
1
2 R
2
C
2
----------------------------------
=
(EQ. 5)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M1M100K10K1K10010
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
F
LC
F
ESR
COMPENSATION
GAIN (dB)
FREQUENCY (Hz)
GAIN
MODULATOR
GAIN
LOOP GAIN
20
V
IN
V
OSC
----------------



log
20
R2
R1
--------


log
ISL6439, ISL6439A
11
FN9057.6
September 15, 2015
capacitor. A conservative approach is presented in
Equation 6.
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern digital ICs can produce high transient load slew
rates. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the expressions in Equation 7:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6439 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The expressions
in Equation 8 give the approximate response time interval for
application and removal of a transient load:
where: I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q
1
turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q
1
and the source of Q
2
.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
The maximum RMS current required by the regulator may be
closely approximated through Equation 9:
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
C
PUMP
I
BiasAndGate
V
CC
f
s
------------------------------------
1.5=
(EQ. 6)
I=
V
IN
- V
OUT
f
s
x L
V
OUT
V
IN
V
OUT
= I x ESR
x
(EQ. 7)
t
RISE
=
L x I
TRAN
V
IN
- V
OUT
t
FALL
=
L x I
TRAN
V
OUT
(EQ. 8)
I
RMS
MAX
V
OUT
V
IN
--------------
I
OUT
MAX
2
1
12
------
V
IN
V
OUT
Lf
s
-----------------------------
V
OUT
V
IN
--------------


2
+


=
(EQ. 9)
ISL6439, ISL6439A
12
FN9057.6
September 15, 2015
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The ISL6439 requires two N-Channel power MOSFETs.
These should be selected based upon r
DS(ON)
, gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor. The switching
losses seen when sourcing current will be different from the
switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching
losses. The lower switch realizes most of the switching losses
when the converter is sinking current (see equations on next
page). These equations assume linear voltage-current
transitions and do not adequately model power loss due the
reverse-recovery of the upper and lower MOSFET’s body
diode. The gate-charge losses are dissipated by the ISL6439
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t
SW
which increases the
MOSFET
switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Given the reduced available gate bias voltage (5V), logic-
level or sub-logic-level transistors should be used for both N-
MOSFETs. Caution should be exercised with devices
exhibiting very low V
GS(ON)
characteristics. The shoot-
through protection present aboard the ISL6439 may be
circumvented by these MOSFETs if they have large parasitic
impedences and/or capacitances that would inhibit the gate
of the MOSFET from being discharged below its threshold
level before the complementary MOSFET is turned on.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 7. The
boot capacitor, C
BOOT
, develops a floating supply voltage
referenced to the PHASE pin. This supply is refreshed each
cycle, when D
BOOT
conducts, to a voltage of CPVOUT less
the boot diode drop, V
D
, plus the voltage rise across
Q
LOWER
.
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
upper MOSFET as shown:
where Q
GATE
is the maximum total gate charge of the upper
MOSFET, C
BOOT
is the bootstrap capacitance, V
BOOT1
is
the bootstrap voltage immediately before turn-on, and
V
BOOT2
is the bootstrap voltage immediately after turn-on.
The bootstrap capacitor begins its refresh cycle when the gate
drive begins to turn-off the upper MOSFET. A refresh cycle
ends when the upper MOSFET is turned on again, which
varies depending on the switching frequency and duty cycle.
The minimum bootstrap capacitance can be calculated by
rearranging the Equation 10 and solving for C
BOOT
.
Typical gate charge values for MOSFETs considered in
these types of applications range from 20nC to 100nC.
Since the voltage drop across Q
LOWER
is negligible,
V
BOOT1
is simply V
CPVOUT
- V
D
. A schottky diode is
P
LOWER
= Io
2
x r
DS(ON)
x (1 - D)
Where: D is the duty cycle = V
OUT
/ V
IN
,
t
SW
is the combined switch ON and OFF time, and
f
s
is the switching frequency.
Losses while Sourcing current
Losses while Sinking current
P
LOWER
Io
2
r
DS ON
1D
1
2
---
Io V
IN
t
SW
f
s
+=
P
UPPER
Io
2
r
DS ON
D
1
2
---
Io V
IN
t
SW
f
s
+=
P
UPPER
= Io
2
x r
DS(ON)
x D
ISL6439
GND
LGATE
UGATE
PHASE
BOOT
V
IN
NOTE:
NOTE:
V
G-S
= V
CC
C
BOOT
D
BOOT
Q
UPPER
Q
LOWER
+
-
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
V
G-S
= V
CC
-V
D
+
V
D
-
CPVOUT
Q
GATE
C
BOOT
V
BOOT1
V
BOOT2
=
(EQ. 10)
C
BOOT
Q
GATE
V
BOOT1
V
BOOT2
-----------------------------------------------------
=
(EQ. 11)
ISL6439, ISL6439A

ISL6439CB-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC REG CTRLR BUCK 14SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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