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ISL6439CB-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
13
FN9057.6
September 15, 2015
recommended to minimize the voltage drop across the
bootstrap capacitor during the on-time of the upper
MOSFET. Initial calculations with V
BOOT2
no less than 4V
will quickly help narrow the bootstrap capacitor range.
For example, consider an upper MOSFET is chosen with a
maximum gate charge, Q
g
, of 100nC. Limiting the voltage
drop across the bootstrap capacitor to 1V results in a value
of no less than 0.1F. The tolerance of the ceramic capacitor
should also be considered when selecting the final bootstrap
capacitance value.
A fast recovery diode is recommended when selecting a
bootstrap diode to reduce the impact of reverse recovery
charge loss. Otherwise, the recovery charge, Q
RR
, would
have to be added to the gate charge of the MOSFET and
taken into consideration when calculating the minimum
bootstrap capacitance.
ISL6439 DC/DC Converter Application
Circuit
Figure 8 shows an application circuit of a DC/DC Converter.
Detailed information on the circuit, including a complete
Bill-of-Materials and circuit board description, can be found
in the ISL6439 Application Note.
Component Selection Notes:
C
3,8,9
- Each 150F, Panasonic EEF-UE0J151R or Equivalent.
D1 - 30mA Schottky Diode, MA732 or Equivalent
L
1
- 1H Inductor, Panasonic P/N ETQ-P6F1ROSFA or Equivalent.
Q
1
- Fairchild MOSFET; ITF86110DK8.
2.5V @ 5A
FBCOMP
UGATE
PHASE
BOOT
GND
LGATE
ISL6439
R
3
R
5
C
10
C
11
R
2
L
1
D
1
C
7
C
1
C
4
C
6
C
8,9
OCSET
CPVOUT
C
3
R
1
Q
1
CT1
CT2
CPGND
VCC
3.3V
C
5
C
2
C
12
R
4
GND
U
1
GND
14
1
2
3
4
5
8
6
7
9
10
11
12
13
TP
1
TP
3
ENABLE
9.76k
6.49k
2.26k
124
0.1F
1000pF
10F
0.22F
1F
0.1F
33pF
5600pF
8200pF
1.07k
Ceramic
ENABLE
FIGURE 8. 3.3V to 2.5V 5A DC/DC CONVERTER
ISL6439, ISL6439A
14
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9057.6
September 15, 2015
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com
.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE REVISION CHANGE
September 15, 2015 FN9057.6 Updated Ordering Information on page 2.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing M14.15 to the latest revision changes are as follows:
-Add land pattern and moved dimensions from table onto drawing.
ISL6439, ISL6439A
15
FN9057.6
September 15, 2015
ISL6439, ISL6439A
Package Outline Drawing
L16.5x5B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 02/08
located within the zone indicated. The pin #1 identifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
0.15(4X)
INDEX AREA
PIN 1
6
5.00
5.00
B
A
PIN #1 INDEX AREA
1613
4X
0.80
12X
2.4
6
4
3 . 10 ± 0 . 15
1
CBA0.10 M
0.33 +0.07 / -0.05
4
5
16X 0 . 60
8
9
12
1.00 MAX
BASE PLANE
SEATING PLANE
0.08
SEE DETAIL "X"
0.10
C
C
C
0 . 00 MIN.
0 . 05 MAX.
0 . 2 REFC
5
( 4 . 6 TYP )
( 3 . 10 )
( 16X 0 .33 )
( 16 X 0 . 8 )
( 12X 0 . 80 )
+0.15
-0.10
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ISL6439CB-T

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