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87332AMI-01LF

P1-P3P4-P6P7-P9P10-P12P13-P14
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
87332AMI-01 DATA SHEET
4 REVISION C 2/12/15
TABLE 4. AC CHARACTERISTICS, V
CC
= 2.375V TO 3.8V, V
EE
= 0, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Input Frequency 1 GHz
t
PD
Propagation Delay; NOTE 1
ƒ ≤ 1GHz
1.1 1.4 1.6 ns
tsk(pp) Part-to-Part Skew; NOTE 2, 3 400 ps
t
R
Output Rise Time 20% to 80% 200 700 ps
t
F
Output Fall Time 20% to 80% 200 700 ps
odc Output Duty Cycle 49 51 %
NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet
specifi cations after thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.
TABLE 3D. LVPECL DC CHARACTERISTICS, V
CC
= 2.375V TO 3.8V, V
EE
= 0, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CC
- 1.4 V
CC
- 0.9 V
V
OL
Output Low Voltage; NOTE 1 V
CC
- 2.0 V
CC
- 1.7 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.65 1.0 V
NOTE 1: Outputs terminated with 50Ω to V
CC
- 2V.
REVISION C 2/12/15
87332AMI-01 DATA SHEET
5 ÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
PARAMETER MEASUREMENT INFORMATION
OUTPUT RISE/FALL TIME
DIFFERENTIAL INPUT LEVEL
3.3V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
87332AMI-01 DATA SHEET
6 REVISION C 2/12/15
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept single
ended levels. The reference voltage V_REF = V
CC
/2 is generated by
the bias resistors R1, R2 and C1. This bias circuit should be located
as close as possible to the input pin. The ratio of R1 and R2 might
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
FIGURE 3B. LVPECL OUTPUT T ERMINATIONFIGURE 3A. LVPECL OUTPUT T ERMINATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
need to be adjusted to position the V_REF in the center of the input
voltage swing. For example, if the input clock swing is only 2.5V and
V
CC
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VCC
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_
P1-P3P4-P6P7-P9P10-P12P13-P14

87332AMI-01LF

Mfr. #:
Buy 87332AMI-01LF
Manufacturer:
IDT
Description:
Clock Generators & Support Products Differential to 2.5V /3.3V ECL/LVPECL Clo
Lifecycle:
New from this manufacturer.
Delivery:
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