REVISION C 2/12/15
87332AMI-01 DATA SHEET
9 ÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 87332I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 87332I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.8V * 30mA = 114mW
• Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.8V, with all outputs switching) = 114mW + 30mW = 144mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature for HiPerClockS
TM
devices is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C
ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used
. Assuming a
moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.144W * 103.3°C/W = 99.9°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (multi-layer).
θ
JA
by Velocity (Linear Feet per Minute)
TABLE 5. THERMAL RESISTANCE θ
JA
FOR 8-PIN SOIC, FORCED CONVECTION
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
