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96D3-1G1333NN-TR1

P1-P3P4-P6P7-P9P10-P10
T
T
T
S
S
S
2
2
2
K
K
K
N
N
N
U
U
U
2
2
2
8
8
8
1
1
1
0
0
0
0
0
0
-
-
-
3
3
3
S
S
S
240PIN DDR3 1333 UDIMM
1024MB With 128Mx8 CL9
Transcend Information Inc.
4
Block Diagram
/D QS1
DQ S 1
DM 1
DQ 8
DQ 9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D 0
D
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/C
S
DQ S /D Q S
D
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/C
S
DQ S /D Q S
D
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/C
S
DQ S /D Q S
D
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/C
S
DQ S /D Q S
/D Q S 0
D Q S0
D M 0
D1
D2
D3
DQ
16
DQ
17
DQ
18
DQ
19
DQ
20
DQ
21
DQ
22
DQ
23
DQ
24
DQ
25
DQ
26
DQ
27
DQ
28
DQ
29
DQ
30
DQ
31
/D QS2
DQ S 2
DM 2
/D QS3
DQ S 3
DM 3
/D Q S 5
DQ S 5
DM 5
DQ
40
DQ
41
DQ
42
DQ
43
DQ
44
DQ
45
DQ
46
DQ
47
D
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/C
S
D Q S/D Q S
D
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/C
S
D Q S/D Q S
D
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/C
S
D Q S/D Q S
/D Q S 4
DQ S 4
DM 4
D 5
D 6
D 7
DQ
48
DQ
49
DQ
50
DQ
51
DQ
52
DQ
53
DQ
54
DQ
55
DQ
56
DQ
57
DQ
58
DQ
59
DQ
60
DQ
61
DQ
62
DQ
63
/D Q S 6
DQ S 6
DM 6
/D Q S 7
DQ S 7
DM 7
D
M
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/C
S
D Q S/D Q S
D 4
D Q
32
D Q
33
D Q
34
D Q
35
D Q
36
D Q
37
D Q
38
D Q
39
BA 0~BA 2
A0~ A15
C KE0
/R AS
/C AS
/W E
OD T 0
C K0
/C K0
BA 0–B A2: SD RA M s D 0–D 7
A0-A15 : SD RA M s D 0–D 7
C KE: S DR AM s D 0–D 7
/R AS : SD RA M s D0–D7
/C AS : SD RA M s D0–D7
/W E : SD RA M s D 0–D 7
OD T : SD RA M s D 0–D 7
C K: S DR AM s D 0–D 7
/C K: S D RA Ms D0–D 7
VD D SP
D
VDD/V D D Q
VREFD
Q
VS
S
EE P R O
M
VREF C
A
D0~D 7
D0~D 7
D0~D 7
D0~D 7
N O T E:
D Q -to-I/O w iring is show n as recomm ended bu t m ay b e
changed.
D Q ,DQ S ,/D Q S ,O D T ,DM ,CKE,/S relationships m ust be
m a intained as shown.
D Q ,DM ,D Q S,/DQ S resistors: R efer to associated topolo gy
diagram
.
1.
2.
3.
SD
A
SC
L
EEPR O
M
W P
A1
A0 A 2
SA 0SA 1
SA 2
/S0
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes
in specifications at any time without prior notice.
T
T
T
S
S
S
2
2
2
K
K
K
N
N
N
U
U
U
2
2
2
8
8
8
1
1
1
0
0
0
0
0
0
-
-
-
3
3
3
S
S
S
240PIN DDR3 1333 UDIMM
1024MB With 128Mx8 CL9
Transcend Information Inc.
5
Operating Temperature Condition
Parameter Symbol
Rating
Unit
Note
Operating Temperature TOPER
0 to 85 °C
1,2
1.Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51.2 standard.
Note:
2. At 0 - 85°C, operation temperature range are the temperature which all DRAM specification will be
supported.
Absolute Maximum DC Ratings
Parameter Symbol Value Unit
Note
s
Voltage on V
DD
relative to Vss VDD -0.4 ~ 1.975 V 1
Voltage on V
DDQ
pin relative to Vss VDDQ -0.4 ~ 1.975 V 1
Voltage on any pin relative to Vss VIN, VOUT -0.4 ~ 1.975 V 1
Storage temperature T
STG
-55~+100 °C 1,2
1.Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Note:
2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC operating conditions (SSTL –1.5)
Rating
Parameter Symbol
Min Typ. Max
Unit
Note
s
Supply voltage VDD 1.425 1.5 1.575 V
1, 2
Supply voltage for Output VDDQ 1.425 1.5 1.575 V
1, 2
I/O Reference Voltage (DQ) VREF
DQ
(DC)
0.49*VDDQ
0.50*VDDQ
0.51*VDDQ V
3, 4
I/O Reference Voltage (CMD/ADD) VREF
CA
(DC)
0.49*VDDQ
0.50*VDDQ
0.51*VDDQ V
3, 4
AC Input Logic High VIH
(AC)
VREF+0.175
- - V
AC Input Logic Low VIL
(AC)
- - VREF-0.175
V
DC Input Logic High VIH
(DC)
V
REF
+0.1 - VDD V
DC Input Logic Low VIL
(DC)
VSS - V
REF
-0.1 V
There is no specific device VDD supply voltage requirement for SSTL-1.5 compliance.
1.Under all conditions VDDQ must be less than or equal to VDD.
Note:
2.VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together.
3.Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD.
AC Input Level for Differential Signals
Parameter Symbol Value Unit Note
Differential Input Logical High V
IHdiff
+200 -
Differential Input Logical Low V
ILdiff
- -200
mV
T
T
T
S
S
S
2
2
2
K
K
K
N
N
N
U
U
U
2
2
2
8
8
8
1
1
1
0
0
0
0
0
0
-
-
-
3
3
3
S
S
S
240PIN DDR3 1333 UDIMM
1024MB With 128Mx8 CL9
Transcend Information Inc.
6
IDD Specification parameters Definition
( IDD values are for full operating range of Voltage and Temperature)
Parameter Symbol
Max.
Unit
Note
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),
tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD0 1,000
mA
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 8, CL =
CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W
IDD1
1,200
mA
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2P
200
mA
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
IDD2Q
560
mA
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is
HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD2N
600
mA
Active power - down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other
control and address bus inputs are STABLE; Data bus inputs are FLOATING
IDD3P
440
mA
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control
and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD3N
720
mA
Operating burst read current; All banks open, Continuous burst reads, IOUT =
0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as IDD4W
IDD4R
2,000
mA
Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL
= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is
HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING IDD4R
IDD4W
2,200
mA
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD5
2,320
mA
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and address
bus inputs are FLOATING; Data bus inputs are FLOATING
IDD6
40
mA
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA;
BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc
= tRC(IDD),
tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid
commands;Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R;
IDD7
4,320
mA
Note: 1. Module I
DD
was calculated on the basis of component I
DD
and can be differently measured according to DQ
loading capacitor.
P1-P3P4-P6P7-P9P10-P10

96D3-1G1333NN-TR1

Mfr. #:
Buy 96D3-1G1333NN-TR1
Manufacturer:
Advantech
Description:
Memory Modules 1G DDR3-1333 240PIN 128X8 SAM(G)
Lifecycle:
New from this manufacturer.
Delivery:
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