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96D3-1G1333NN-TR1

P1-P3P4-P6P7-P9P10-P10
T
T
T
S
S
S
2
2
2
K
K
K
N
N
N
U
U
U
2
2
2
8
8
8
1
1
1
0
0
0
0
0
0
-
-
-
3
3
3
S
S
S
240PIN DDR3 1333 UDIMM
1024MB With 128Mx8 CL9
Transcend Information Inc.
7
Timing Parameters & Specifications
Parameter Symbol
Min Max Unit Note
Average Clock Period, CL=9, CWL=7
tCK 1.5 <1.875 ns
Average high pulse width
tCH 0.47 0.53 tCK
Average low pulse width tCL 0.47 0.53 tCK
DQS, /DQS to DQ skew, per group, per access
tDQSQ - 125 ps
DQ output hold time from DQS, /DQS
tQH 0.38 - tCK
DQ low-impedance time from CK, /CK
tLZ(DQ)
-500 250
ps
DQ high-impedance time from CK, /CK
tHZ(DQ)
- 250
ps
Data setup time to DQS, /DQS reference to
Vih(ac)Vil(ac) levels
tDS TBD - ps
Data hold time to DQS, /DQS reference to
Vih(ac)Vil(ac) levels
tDH TBD -
ps
DQ and DM input pulse width for each input
tDIPW 400 - ps
DQS, /DQS Write preamble
tWPRE 0.9 - tCK
DQS, /DQS Write postamble
tWPST 0.3 - tCK
DQS, /DQS low-impedance time
tLZ(DQS)
-600 300 Ps
DQS, /DQS high-impedance time
tHZ(DQS)
- 300 ps
DQS, /DQS differential input low pulse width
tDQSL 0.4 0.6 tCK
DQS, /DQS differential input high pulse width
tDQSH 0.4 0.6 tCK
DQS, /DQS rising edge to CK, /CK rising edge
tDQSS -0.25 +0.25 tCK
DQS, /DQS falling edge setup time to CK, /CK rising
edge
tDSS
0.2 -
tCK
DQS, /DQS falling edge hold time to CK, /CK rising
edge
tDSH 0.2 - tCK
Delay from start of Internal write transaction to Internal
read command
tWTR
Max
(4tck, 7.5ns)
-
Write recovery time tWR
15 -
ns
Mode register set command cycle time
tMRD 4 - tCK
/CAS to /CAS command delay
tCCD
4 - nCK
Auto precharge write recovery + precharge time tDAL
tWR+tRP/tck nCK
Active to active command period for 1KB page size
tRRD
Max
(4tck, 7.5)
- ns
Active to active command period for 2KB page size
tRRD
Max
(4tck, 10)
- ns
Four Activate Window for 1KB page size products
tFAW 30 - ns
Four Activate Window for 2KB page size products
tFAW 45 - ns
Power-up and RESET calibration time
tZQinitl
512 - tCK
T
T
T
S
S
S
2
2
2
K
K
K
N
N
N
U
U
U
2
2
2
8
8
8
1
1
1
0
0
0
0
0
0
-
-
-
3
3
3
S
S
S
240PIN DDR3 1333 UDIMM
1024MB With 128Mx8 CL9
Transcend Information Inc.
8
Normal operation Full calibration time tZQoper
256 -
tCK
Normal operation short calibration time tZQcs 64
- tCK
Exit self refresh to commands not requiring a locked
DLL
tXS
Max
(5tCK,
tRFC+10)
-
ns
Exit self refresh to commands requiring a locked DLL tXSDLL
tDLL(min) - tCK
Internal read to precharge command delay tRTP
7.5 -
ns
Minimum CKE low width for Self refresh entry to exit
timing
tCKESR
tCK(min)+1tCK
-
-
Exit power down with DLL to any valid command: Exit
Precharge Power Down with DLL
tXP
Max
(3tCK, 7.5ns)
-
-
CKE minimum pulse width (high and low pulse width) tCKE
Max
(3tCK, 5.62ns)
-
Asynchronous RTT turn-on delay (Power-Down mode)
tAONPD
1 9
ns
Asynchronous RTT turn-off delay (Power-Down mode)
tAOFPD
1 9 ns
ODT turn-on tAON -300 30
ps
ODT turn-off tAOF 0.3 0.7
tCK
T
T
T
S
S
S
2
2
2
K
K
K
N
N
N
U
U
U
2
2
2
8
8
8
1
1
1
0
0
0
0
0
0
-
-
-
3
3
3
S
S
S
240PIN DDR3 1333 UDIMM
1024MB With 128Mx8 CL9
Transcend Information Inc.
9
SERIAL PRESENCE DETECT SPECIFICATION
Serial Presence Detect
Byte No.
Function Described Standard Specification
Vendor Part
0
Number of SPD Bytes written / SPD device size / CRC
coverage during module production
CRC:0-116Byte
SPD Byte use: 176Byte
SPD Byte total: 256Byte
92
1 SPD Revision Version 0.5 05
2 Key Byte / DRAM Device Type DDR3 SDRAM 0B
3 Key Byte / Module Type UDIMM 02
4 SDRAM Density and Banks 1GB 8banks 02
5 SDRAM Addressing ROW:14, Column:10 11
6 Reserved - 00
7
Module Organization
1Rank / x8 01
8 Module Memory Bus Width Non ECC, 64bit 03
9
Fine Timebase Dividend and Divisor
2.5ps 52
10
Medium Timebase Dividend
0.125ns 01
11 Medium Timebase Divisor 0.125ns 08
12 SDRAM Minimum Cycle Time (tCKmin) 1.5ns 0C
13 Reserved - 00
14 CAS Latencies Supported, Least Significant Byte 6, 7, 8, 9 3C
15 CAS Latencies Supported, Most Significant Byte 6, 7, 8, 9 00
16
Minimum CAS Latency Time (tAAmin)
13.5ns 6C
17
Minimum Write Recovery Time (tWRmin)
15ns 78
18 Minimum /RAS to /CAS Delay Time (tRCDmin) 13.5ns 6C
19
Minimum Row Active to Row Active Delay Time
(tRRDmin)
6ns 30
20
Minimum Row Precharge Time (tRPmin)
13.5ns 6C
21 Upper Nibble for tRAS and tRC
-
11
22 Minmum Active to Precharge Time (tRASmin) 36ns 2C
23 Minmum Active to Active/Refresh Time (tRCmin) 49.5ns 8C
24
Minmum Refresh Recovery Time (tRFCmin), Least
Significant Byte
110ns 70
25
Minmum Refresh Recovery Time (tRFCmin), Most
Significant Byte
110ns 03
26
Minmum Internal Write to Read Command Delay Time
(tWTmin)
7.5ns 3C
27
Minimum Internal Read to Precharge Command Delay
Time (tRTPmin)
7.5ns 3C
28 Upper Nibble for tFAW 30ns 00
29 Minmum Four Active Window Delay Time (tFAWmin) 30ns F0
30 SDRAM Optional Features
DLL off Mode,
RZQ/6, RZQ/7
83
31 SDRAM Thermal and Refresh Options No ODTs, No ASR 01
32-59
Reserved
- 00
60
Module Nominal Height
30mm 0F
61
Module Max Thickness
Planar Single Sides 01
P1-P3P4-P6P7-P9P10-P10

96D3-1G1333NN-TR1

Mfr. #:
Buy 96D3-1G1333NN-TR1
Manufacturer:
Advantech
Description:
Memory Modules 1G DDR3-1333 240PIN 128X8 SAM(G)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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