Data Sheet ADG5436
Rev. B | Page 15 of 19
INx
V
OUT
Dx
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SxB
V
IN
V
S
0.1µF0.1µF
R
L
300Ω
50%
50%
90%
50%
50%
90%
t
ON
t
OFF
V
IN
V
OUT
V
IN
09204-026
Figure 31. Switching Times
INx
V
OUT
Dx
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SxB
V
IN
V
S
0.1µF
0.1µF
R
L
300Ω
80%
t
D
t
D
V
OUT
V
IN
09204-027
Figure 32. Break-Before-Make Time Delay t
D
OUTPUT
INx
50Ω
300Ω
GND
SxA
SxB
Dx
35pF
V
IN
EN
V
DD
V
SS
V
DD
V
SS
V
S
3V
0V
OUTPUT
50% 50%
t
OFF
(EN)
t
ON
(EN)
0.9V
OUT
0.9V
OUT
ENABLE
DRIVE (V
IN
)
09204-028
Figure 33. Enable Delay, t
ON
(EN), t
OFF
(EN)
V
IN
(NORMALLY
CLOSED SWITCH)
V
OUT
V
IN
(NORMALLY
OPEN SWITCH)
OFF
ΔV
OUT
ON
Q
INJ
= C
L
× ΔV
OUT
INx
V
OUT
Dx
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
1nF
NC
SxB
V
IN
V
S
0.1µF0.1µF
09204-029
Figure 34. Charge Injection
ADG5436 Data Sheet
Rev. B | Page 16 of 19
TERMINOLOGY
I
DD
I
DD
represents the positive supply current.
I
SS
I
SS
represents the negative supply current.
V
D
, V
S
V
D
and V
S
represent the analog voltage on Terminal D and
Terminal S, respectively.
R
ON
R
ON
represents the ohmic resistance between Terminal D and
Terminal S.
∆R
ON
∆R
ON
represents the difference between the R
ON
of any two
channels.
R
FLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range is represented by R
FLAT (ON)
.
I
S
(Off)
I
S
(Off) is the source leakage current with the switch off.
I
D
(Off)
I
D
(Off) is the drain leakage current with the switch off.
I
D
(On), I
S
(On)
I
D
(On) and I
S
(On) represent the channel leakage currents with
the switch on.
V
INL
V
INL
is the maximum input voltage for Logic 0.
V
INH
V
INH
is the minimum input voltage for Logic 1.
I
INL
, I
INH
I
INL
and I
INH
represent the low and high input currents of the
digital inputs.
C
D
(Off)
C
D
(Off) represents the off switch drain capacitance, which is
measured with reference to ground.
C
S
(Off)
C
S
(Off) represents the off switch source capacitance, which is
measured with reference to ground.
C
D
(On), C
S
(On)
C
D
(On) and C
S
(On) represent on switch capacitances, which
are measured with reference to ground.
C
IN
C
IN
is the digital input capacitance.
t
ON
t
ON
represents the delay between applying the digital control
input and the output switching on.
t
OFF
t
OFF
represents the delay between applying the digital control
input and the output switching off.
t
D
t
D
represents the off time measured between the 80% point of
both switches when switching from one address state to
another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental is represented by THD + N.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. This is a measure of the ability of
the part to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.
Data Sheet ADG5436
Rev. B | Page 17 of 19
TRENCH ISOLATION
In the ADG5436, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction isolated switches, are eliminated, and the result is a
completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors form a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
can become forward-biased. A silicon controlled rectifier (SCR)
type circuit is formed by the two transistors causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed, and the result is a latch-up
proof switch.
09204-045
NMOS PMOS
P-WELL N-WELL
BURIED OXIDE LAYER
HANDLE WAFER
TRENCH
Figure 35. Trench Isolation

EVAL-ADG5436FEBZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Switch IC Development Tools EVALUATION BOARD I.C.
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