OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NCP5424DG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
NCP5424
http://onsemi.com
13
P
RMS(H)
I
RMS(H)
2
R
DS(ON)
where:
P
RMS(H)
= switching MOSFET conduction losses;
I
RMS(H)
= maximum switching MOSFET RMS current;
R
DS(ON)
= FET drain−to−source on−resistance
The upper MOSFET switching losses are caused during
MOSFET switch−on and switch−off and can be determined
by using the following formula:
P
SWH
P
SWH(ON)
P
SWH(OFF)
V
IN
I
OUT
(t
RISE
t
FALL
)
6T
where:
P
SWH(ON)
= upper MOSFET switch−on losses;
P
SWH(OFF)
= upper MOSFET switch−off losses;
V
IN
= input voltage;
I
OUT
= load current;
t
RISE
= MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
t
FALL
= MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
T = 1/f
SW
= period.
The total power dissipation in the switching MOSFET can
then be calculated as:
P
HFET(TOTAL)
P
RMS(H)
P
SWH(ON)
P
SWH(OFF)
where:
P
HFET(TOTAL)
= total switching (upper) MOSFET losses;
P
RMS(H)
= upper MOSFET switch conduction Losses;
P
SWH(ON)
= upper MOSFET switch−on losses;
P
SWH(OFF)
= upper MOSFET switch−off losses;
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
T
J
T
A
[P
HFET(TOTAL)
R
JA
]
where:
T
J
= FET junction temperature;
T
A
= ambient temperature;
P
HFET(TOTAL)
= total switching (upper) FET losses;
R
JA
= upper FET junction−to−ambient thermal resistance.
Selection of the Synchronous (Lower) FET
The switch conduction losses for the lower FET can be
calculated as follows:
[I
OUT
(1 D)
]
2
R
DS(ON)
P
RMS(L)
I
RMS
2
R
DS(ON)
where:
P
RMS(L)
= lower MOSFET conduction losses;
I
OUT
= load current;
D = Duty Cycle;
R
DS(ON)
= lower FET drain−to−source on−resistance.
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non−overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
P
SWL
V
SD
I
LOAD
non−overlap time f
SW
where:
P
SWL
= lower FET switching losses;
V
SD
= lower FET source−to−drain voltage;
I
LOAD
= load current;
Non−overlap time = GATE(L)−to−GATE(H) or
GATE(H)−to−GATE(L) delay (from NCP5424 data sheet
Electrical Characteristics section);
f
SW
= switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
P
LFET(TOTAL)
P
RMS(L)
P
SWL
where:
P
LFET(TOTAL)
= Synchronous (lower) FET total losses;
P
RMS(L)
= Switch Conduction Losses;
P
SWL
= Switching losses.
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
T
J
T
A
[P
LFET(TOTAL)
R
JA
]
where:
T
J
= MOSFET junction temperature;
T
A
= ambient temperature;
P
LFET(TOTAL)
= total synchronous (lower) FET losses;
R
JA
= lower FET junction−to−ambient thermal resistance.
Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, V
CC
, and the NCP5424 operating frequency. The
average MOSFET gate charge current typically dominates
the control IC power dissipation.
The IC power dissipation is determined by the formula:
P
GATE(L)1
P
GATE(H)2
P
GATE(L)2
P
CONTROL(IC)
I
CC1
V
CC1
I
BST
V
BST
P
GATE(H)1
where:
P
CONTROL(IC)
= control IC power dissipation;
I
CC1
= IC quiescent supply current;
V
CC1
= IC supply voltage;
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
P
GATE(L)
= lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses
are:
P
GATE(H)
Q
GATE(H)
f
SW
V
BST
where:
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
Q
GATE(H)
= total upper MOSFET gate charge at V
CC
;
f
SW
= switching frequency;
The lower (synchronous) MOSFET gate driver (IC)
losses are:
P
GATE(L)
Q
GATE(L)
f
SW
V
CC
NCP5424
http://onsemi.com
14
where:
P
GATE(L)
= lower MOSFET gate driver (IC) losses;
Q
GATE(L)
= total lower MOSFET gate charge at V
CC
;
f
SW
= switching frequency;
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
Selection of the Current Sharing Ratio
When the two controllers are connected together as a
single output two−phase Buck Converter, the two
controllers are in a Master−Slave configuration. The Slave
controller on the right side of Figure 1 tries to follow
information provided by the Master controller, on the left.
The circuit uses inductor current sensing, in which the
parasitic resistance (LSR) of the controller’s output chokes
are used as a current sensing element. On the Slave side
(Controller Two), both Error Amplifier inputs are brought to
external pins so the reference is available. The RC network
in parallel with the output inductor on the Master side
(Controller One) generates the reference for the Slave.
Current information from the Slave is fed back to the error
amplifier’s inverting input. In this configuration, the Slave
tries to adjust its current to match the current information fed
to its reference input from the Master Controller. In Figure 1,
R1, R2 and C6 are used to generate the Slave’s reference.
R17 and C14 generate the Slave’s inverting input signal. If
50−50 current sharing is needed, then only R2 and C6 are
required to generate the reference signal. The values for both
sides should be calculated with the following equation.
R
L
C6 · RL
where:
L = Inductor value, both Controllers should use the
same inductor.
RL = Internal resistance of L, from inductor data sheet.
C6 = Select a value such that R < 15 k.
With the RC time constant selected to equal the L/R
L
time
constant, the voltage across the capacitor will be equal to the
voltage drop across the internal resistance of the inductor. For
proper sharing, the inductors on both sides should be the same.
If a ratio other than 50−50 is needed, the R and C values
of the inverting signal filter are calculated using the previous
equation. Since the reference signal has to be divided down
to the proper ratio, R1 is required. Using the same
capacitance value, the following equation is used to
calculate the proper values for the reference filter.
R2
R1(1 Ratio)
Ratio
where:
R1 = Chosen Value, 10 k is recommended.
Ratio
%slave
%master
, input power ratio
To ensure greater accuracy, the equivalent parallel
resistance of R1 and R2 should be greater or equal to the value
R17, the resistance value calculated for the inverting signal.
R17
R1 · R2
R1 R2
R17 = The inverting signal filter resistance.
Current Sharing Errors
The three main errors in current sharing arise from board
layout imbalances, inductor mismatch, and input offsets in
the error amplifiers. The first two sources of error can be
controlled through careful component selection and good
layout practice. With a 4.0 m inductor, for example, one
mV of input offset error will represent .25 A of error. One
way to diminish this effect is to use higher resistance
inductors but the penalty is higher power losses in the
inductors. Fortunately, the input offset of the NCP5424 is
low so that this error term is reduced.
Current Sharing Compensation Capacitor Selection
The NCP5424 is designed for single and dual output
applications. Therefore the IC needs two separate
compensation capacitors for the dual output designs, which
is not desirable for a single output design. With two
compensation capacitors, a race condition between the
master and slave controllers is created. During start−up or
upon leaving Hiccup mode, the Master’s Error Amplifier
starts charging Comp1. When Comp1 reaches 0.40 V, both
controllers begin to regulate the output. The Slave
Controller voltage reference is generated externally by the
Master’s output, while the Master has an internal 1.0 V
reference. Since Comp2 does not start charging until Comp1
reaches 0.40 V, the Slave’s PWM inverting input is lower
than its Vfb−2 input causing a reset of the Slave Controller
output driver. Gate(L)2 turns on, sinking current from the
output, while the Master’s output driver is set turning
Gate(H)1 on and sourcing current to the output (since its
PWM inverting input is higher than its Vfb1 input). This
condition will continue until Comp2’s amplitude is equal to
Comp1’s. During this condition, the output voltage is being
shorted to ground through the bottom FET, on the slave side.
In hiccup mode, if this shoot−through current is large
enough to develop 70 mV across L1, the Controllers will
remain in hiccup mode even after the external load or short
is removed. To avoid this condition, the Comp2 ramp’s rise
time is increased to minimize the shoot−through current.
The value of the Comp2 capacitor is calculated by the
following equations.
R
X
R
L2
R
fet
C13
0.45 · R
L2
(0.07 · 25%) · R
X
1
C8
where:
C8 = Comp1 capacitor value, 0.22 F is suggested.
R
L2
=Inductor parasitic resistance (LSR), see inductor’s
data sheet.
R
fet
=R
DS(on)
of the Slave’s lower FET, see data sheet.
A good rule of thumb is a 20 to 1 ratio between Comp1 and
Comp2. If Soft−Start rise time is not an issue, a 0.22 F
NCP5424
http://onsemi.com
15
capacitor on the Comp1 pin and a 0.01 F capacitor on the
Comp2 pin in suggested.
Selecting Current Sharing Current Limit
In a two−phase single output application, there are two
different current limit options. The Master (Controller One)
current limit can be set equal to the Slave (Controller Two)
which brings both controllers into Hiccup Mode during an
overcurrent condition. The second option is to set Slave
current limit lower than that of the Master, which limits the
Slave’s input power when its limit is reached, while the
output voltage remains in regulation. Both Master and Slave
will go into hiccup mode if the Master’s limit is reached.
During Cycle−By−Cycle current limit, the Slave’s operating
frequency will decrease in half, due to pulse skipping,
resulting in phase overlap. This overlap will increase the
output voltage ripple.
Exceeding 70 mV between the IS+ and IS− pins trips the
current limits. A divided down V
out
signal is used to generate
the IS− reference, and inductor sensing of the controllers
output chokes provide the output current information to
IS+X pin. The inductor sensing is achieved by placing a
series RC in parallel with the output choke. With the RC time
constant selected to equal the L/R
L
time constant, the
voltage across the capacitor will be equal to the voltage drop
across the internal resistance of the inductor.
The resistance of the output choke (LSR) must be known
to calculate the overcurrent trip point. The voltage drop
across the inductor at overcurrent is calculated as follows:
V
L
R
L
·I
out
(eq. 1)
where:
V
L
= Voltage drop across the inductor,
R
L
= LSR of the inductor,
I
out
= Output current trip point for one phase.
For Hiccup Mode only, both sensing networks should have
the identical values.
If the inductor selected has a 5.0 m LSR and the current
limit is 10 A through one of the phases, then the analog
signal will be 50 mV. Since this value is less than 70 mV,
then the IS− divider, R3 and R4 in Figure 1, must scale down
the V
out
by 20 mV, thus placing a 20 mV offset across the IS−
and IS+x pin at no load and allowing the Controllers to trip
into current limit with only 50 mV across the inductor. In
this case, the RC values are calculated using the following
equation:
R
RC
L
C
RC
·R
L
(eq. 2)
L = Inductor value, both Controllers should have the
same value.
R
L
= Internal resistance of L, see data sheet.
C
RC
=Chosen value, 0.1 F will make R a reasonable
value.
And the IS− divider value can be selected with this equation.
R3
V
out
V
out
V
os
1
·R4
(eq. 3)
where:
V
out
= Output regulated voltage.
V
os
= Offset voltage, example above was 20 mV.
R4 = Chosen value, 10 K is a good choice.
If V
os
is larger than 70 mV, then the current signal from the
output chokes must be divided down. For example, if the
inductor’s LSR is equal to 8.0 m and the current limit is
15 A, then the current signal is 120 mV, which is almost
twice the comparator’s offset (70 mV). This signal can be
divided down by adding a resistor (R1) in parallel with the
capacitor (C6) in the inductor sensing network, see Figure 1.
The divider R1 and R2 can be set to equal value to divide the
current signal in half and equation (3) should be used to
select the proper voltage divider. Notice that the divider R1
and R2, divides down the voltage applied to the capacitor
C
RC
by a factor of 2. This divides the voltage across the
output inductor’s LSR by a factor of two and results in twice
the current limit. This scaling technique is another way the
current limit may be set so that virtually any current limit
may be obtained.
To ensure accuracy, the equivalent parallel resistance of
R1 and R2 should be greater or equal to the value R
RC
, the
resistance value calculated from equation (2). If Hiccup
Mode is used, then both sensing network values must be
equal.
If Cycle−by−Cycle is desired, then equation (1), (2) and
(3) should be used to select the Slave’s inductor sensing
network for the desired current limit and equation (4) should
be used to raise the Master’s current limit, Hiccup Mode,
above the Slave’s limit.
R2
R1(1 Ratio)
Ratio
(eq. 4)
where:
R1 = Chosen value, 10 K is recommended,
Ratio
I
slave.limit
I
master.limit
, Master’s and Slave’s current
limit ratio.
To ensure greater accuracy, the equivalent parallel
resistance of R1 and R2 should be greater or equal to the
value R
RC
, value calculated from equation (2).
R
RC
R1·R2
R1 R2
(eq. 5)
Current Sensing
The current supplied to the load can be sensed easily using
the IS+ and IS− pins for the output. These pins sense a
voltage, proportional to the output current, and compare it to
a fixed internal voltage threshold. When the differential
voltage exceeds 70 mV, the internal overcurrent protection
system goes into hiccup mode. Two methods for sensing the
current are available.
Sense Resistor. A sense resistor can be added in series
with the inductor. When the voltage drop across the sense
resistor exceeds the internal voltage threshold of 70 mV, a
fault condition is set.
The sense resistor is selected according to:
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

NCP5424DG

Mfr. #:
Buy NCP5424DG
Manufacturer:
ON Semiconductor
Description:
IC REG CTRLR BUCK 16SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet