PLL Tuned UHF Transmitter for Data Transfer Applications, Rev. 1.7
Transmitter Functional Description
Freescale Semiconductor4
1 Transmitter Functional Description
MC33493 is a PLL-tuned low-power UHF transmitter. The different modes of operation are controlled by the microcontroller
through several digital input pins. The power supply voltage ranges from 1.9 V to 3.6 V, allowing operation with a single lithium
cell.
2 Phase Locked Loop and Local Oscillator
The VCO is a completely integrated relaxation oscillator. The phase frequency detector (PFD) and the loop filter are fully
integrated. The exact output frequency is equal to: f
RFOUT
= f
XTAL
× [PLL divider ratio]. The frequency band of operation is
selected through the BAND pin.
Table 3 shows details for each frequency band selection.
Table 3. Band Selection and Associated Divider Ratios
An out-of-lock function is performed by monitoring the PFD output voltage. When it exceeds defined limits, the RF output stage
is disabled.
3 Radio Frequency (RF) Output Stage
The radio frequentcy (RF) output stage source is a single-ended square-wave switched current. Harmonics are present in the
output current drive. Their radiated absolute level depends on the antenna characteristics and output power. Typical application
demonstrates compliance to ETSI standard.
A resistor, R
ext
, connected to the REXT pin controls the output power allowing a trade-off between radiated power and current
consumption.
The output voltage is internally clamped to V
cc
± 2V
be
(typ. V
cc
± 1.5 V @ T
A
=25 °C).
4 Modulation
To select the On Off Keying (OOK) modulation, a low-logic level must be applied on the MODE pin. This modulation is
performed by switching the RF output stage on or off. The logic level applied on the DATA pin controls the output stage state:
DATA = 0
→ output stage off,
DATA = 1
→ output stage on.
Applying a high-logic level on the MODE pin selects Frequency Shift Keying (FSK) modulation. This modulation is achieved
by crystal pulling. An internal switch connected to the CFSK pin enables switching the external crystal load capacitors. Figure 2
shows the possible configurations: serial and parallel.
The logic level applied on pin DATA controls the state of this internal switch:
DATA=0
→ switch off,
DATA=1
→ switch on.
DATA input is internally re-synchronized by the crystal reference signal. The corresponding jitter on the data duty cycle cannot
exceed ±1 reference period (±75 ns for a 13.56 MHz crystal).
This crystal pulling solution implies that the RF output frequency deviation equals the crystal frequency deviation multiplied
by the PLL Divider ratio (see Table 3).
BAND Input Level
Frequency Band
(MHz)
PLL Divider Ratio
Crystal Oscillator
Frequency (MHz)
High 315
32
9.84
434
13.56
Low 868 64
