IRF9Z34S, SiHF9Z34S
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Vishay Siliconix
S16-0754-Rev. E, 02-May-16
6
Document Number: 91093
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Fig. 14 - For P-Channel
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.
P.W.
Period
dI/dt
Diode recovery
dV/dt
Body diode forward drop
Body diode forward
current
Driver gate drive
Inductor current
D =
P.W.
Period
+
-
-
-
-
+
+
+
Peak Diode Recovery dV/dt Test Circuit
• dV/dt controlled by R
g
• D.U.T. - device under test
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
R
g
• Compliment N-Channel of D.U.T. for driver
V
DD
• I
SD
controlled by duty factor “D”
Note
Note
a. V
GS
= - 5 V for logic level and - 3 V drive devices
V
GS
= - 10 V
a
D.U.T. l
SD
waveform
D.U.T. V
DS
waveform
V
DD
Re-applied
voltage
Ripple ≤ 5 %
I
SD
Reverse
recovery
current