TC850
DS21479D-page 6 2001-2012 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number
(40-Pin
PDIP/CERDIP)
Pin Number
(44-Pin PLCC)
Symbol Description
1 2 CS Chip Select, active HIGH. Logically ANDed, with CE
to enable read and write
inputs (Note 1).
23CE
Chip enable, active LOW (Note 2).
34WR
Write input, active LOW. When chip is selected (CS = HIGH and CE = LOW) and
in Demand mode (CONT/DEMAND
= LOW), a logic LOW on WR starts a
conversion (Note 1).
45RD
Read input, active LOW. When CS = HIGH and CE = LOW, a logic LOW on RD
enables the 3-state data outputs (Note 2).
5 6 CONT/
DEMAND
Conversion control input. When CONT/DEMAND = LOW, conversions are initi-
ated by the WR
input. When CONT/DEMAND = HIGH, conversions are
performed continuously (Note 1).
67OVR/POL
Overrange/polarity data-select input. When making conversions in the Demand
mode (CONT/DEMAND
= LOW), OVR/POL controls the data output on DB7
when the high-order byte is active (Note 2).
78L/H
Low/high byte-select input. When CONT/DEMAND = LOW, this input controls
whether low-byte or high-byte data is enabled on DB0 through DB7 (Note 2).
8 9 DB7 Most Significant data bit output. When reading the A/D conversion result, the
polarity, overrange and DB7 data are output on this pin.
9-15 10-17 DB6-DB0 Data outputs DB6-DB0. 3-state, bus compatible.
16 18 BUSY A/D conversion status output. BUSY goes to a logic HIGH at the beginning of the
de-integrate phase, then goes LOW when conversion is complete. The falling
edge of BUSY can be used to generate a
P interrupt.
17 19 OSC
1
Crystal oscillator connection or external oscillator input.
18 20 OSC
2
Crystal oscillator connection.
19 21 TEST For factory testing purposes only. Do not make external connection to this pin.
20 22 DGND Digital ground connection.
21 24 COMP Connection for comparator auto-zero capacitor. Bypass to V
SS
with 0.1 F.
22 25 V
SS
Negative power supply connection, typically -5V.
23 26 INT
OUT
Output of the integrator amplifier. Connect to C
INT
.
24 27 INT
IN
Input to the integrator amplifier. Connect to summing node of R
INT
and C
INT
.
25 28 BUFFER Output of the input buffer. Connect to R
INT
.
26 29 C
BUFB
Connection for buffer auto-zero capacitor. Bypass to V
SS
with 0.1 F.
27 30 C
BUFA
Connection to buffer auto-zero capacitor. Bypass to V
SS
with 0.1 F.
28 31 C
INTA
Connection for integrator auto-zero capacitor. Bypass to V
SS
with 0.1 F.
29 32 C
INTB
Connection for integrator auto-zero capacitor. Bypass to V
SS
with 0.1 F.
30 33 ANALOG
COMMON
Analog common.
31 35 IN– Negative differential analog input.
32 36 IN+ Positive differential analog input.
Note 1: This pin incorporates a pull-down resistor to DGND.
2: This pin incorporates a pull-up resistor to V
DD
.
3: Pins 1, 23 and 34 (44-PLCC) package are NC “No Internal connection”.
