LTC2365/LTC2366
14
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Figure 10. LTC2365/LTC2366 Serial Interface Timing Diagram
applications inForMation
OVERVIEW
The LTC2365/LTC2366 use a successive approximation
algorithm and internal sample-and-hold circuit to convert
an analog signal to a 12-bit serial output. Both devices
operate from a single 2.35V to 3.6V supply. The LTC2366
samples at a rate of 3Msps with a 48MHz clock while the
LTC2365 samples at a rate of 1Msps with a 16MHz clock.
The LTC2365/LTC2366 contain a 12-bit, switched-capacitor
ADC, a sample-and-hold, and a serial interface (see Block
Diagram) and are available in tiny 6- and 8-lead TSOT-23
packages. The devices provide sleep mode control through
the serial interface to save power during inactive periods
(see the SLEEP MODE section).
The S6 package of the LTC2365/LTC2366 uses V
DD
as the
reference and has an analog input range of 0V to V
DD
. The
ADC samples the analog input with respect to GND and
outputs the result through the serial interface.
The TS8 package provides two additional pins: a reference
input pin, V
REF
, and an output supply pin, OV
DD
. The ADC
can operate with reduced spans down to 1.4V and achieve
342µV resolution. OV
DD
controls the output swing of the
digital output pin, SDO, and allows the device to com-
municate with 1.8V, 2.5V or 3V digital systems.
SERIAL
INTERF
ACE
The LTC2365/LTC2366 communicate with microcon
-
trollers, DSPs and other external circuitry via a 3-wire
interface. Figure 10 shows the serial interface timing dia-
gram, while
Figures 11 and 12 detail the timing diagrams
of
conversion cycles in 14 and 16 SCK cycles, respectively.
Data Transfer
A falling CS edge starts a conversion and frames the se
-
rial data transfer. SCK provides the conversion clock and
controls the data transfer during the conversion.
CS going
LOW clocks out the first leading zero and sub-
sequent SCK falling edges clock out the remaining data,
beginning with the second leading zero. (Therefore, the
first SCK falling edge captures the first leading zero and
clocks out the second leading zero). The timing diagram
in Figure 12 shows that the final bit in the data transfer is
valid on the 16th falling edge, since it is clocked out on
the previous 15th falling edge.
In applications with a slower SCK, it is possible to capture
data on each SCK rising edge. In such cases, the first
falling edge of SCK clocks out the
second leading
zero
and can be captured on the first rising edge. However,
the first leading zero clocked out when CS goes LOW is
missed, as shown in Figures 11 and 12. In Figure 12, the
15th falling edge of SCK clocks out the last bit and can
be captured on the 15th rising SCK edge.
If CS goes LOW while SCK is LOW, then CS clocks out the
first leading zero and can be captured on the SCK rising
edge. The next SCK falling edge clocks out the second
leading zero and can be captured on the following rising
edge, as shown in Figure 10.
1SCK
SDO
t
2
t
3
t
4
t
7
t
5
t
8
ZERO ZERO B11 B10 B9 B1 B0 ZERO ZERO
2 3 4
(MSB)
Hi-Z STATE
5 13 14 15 16
t
6
t
QUIET
t
ACQ
13t
SCK
t
THROUGHPUT
t
CONV
CS
t
1
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