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DD8C32_64x64HD.fm - Rev. E 11/08 EN
10 ©2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x64, DR): 200-Pin DDR SDRAM SODIMM
Electrical Specifications
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are
in I
DD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 10: IDD Specifications and Conditions – 256MB (All other Die Revisons)
Values are for the MT46V16M16 DDR SDRAM only and are computed from values specified in the
256Mb (16 Meg x 16) component data sheet
Parameter/Condition Symbol -40B -335
-26A/
-265
Units
Operating one
device
bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing
once per clock cycle; Address and control inputs changing once every
two clock cycles
IDD0
1
556 516 496 mA
Operating one device bank active-read-precharge current:
Burst = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Iout = 0mA; Address and
control inputs changing once per clock cycle
IDD1
1
756 736 636 mA
Precharge power-down standby current: All device banks idle;
Power-down mode;
t
CK =
t
CK (MIN); CKE = (LOW)
I
DD2P
2
32 32 32 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN); CKE = HIGH; Address and other control inputs
changing once per clock cycle;
VIN
=
VREF
for DQ, DM, and DQS
IDD2F
2
480 400 360 mA
Active power-down standby current: One device bank active;
Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
I
DD3P
2
320 240 200/
240
mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
IDD3N
2
560 480 400 mA
Operating burst read current: Burst = 2; Continuous burst reads;
One device bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK (MIN); Iout = 0mA
I
DD4R
1
1,056 896 756 mA
Operating burst write current: Burst = 2; Continuous burst writes;
One device bank active; Address and control inputs changing once per
clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle
I
DD4W
1
876 796 656 mA
Auto refresh burst current
t
RFC =
t
RFC (MIN)
I
DD5
2
2,080 2,040 1,880/
1,960
mA
t
RFC = 7.8125µs
I
DD5A
2
48 48 48 mA
Self refresh current: CKE ≤ 0.2V
I
DD6
2
32 32 32 mA
Operating bank interleave read current: Four device bank
interleaving reads; (burst = 4) with auto precharge,
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control inputs change only during active
READ or WRITE commands
I
DD7
1
2,056 1,776 1,536/
1,616
mA
