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DD8C32_64x64HD.fm - Rev. E 11/08 EN
9 ©2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x64, DR): 200-Pin DDR SDRAM SODIMM
Electrical Specifications
IDD Specifications
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are
in IDD2P (CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 9: IDD Specifications and Conditions – 256MB (Die Revision K)
Values are for the MT46V16M16 DDR SDRAM only and are computed from values specified in the
256Mb (16 Meg x 16) component data sheet
Parameter/Condition Symbol -40B -335 Units
Operating one
device
bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing once per
clock cycle; Address and control inputs changing once every two clock cycles
IDD0
1
416 376 mA
Operating one device bank active-read-precharge current:
Burst = 4;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle
I
DD1
1
496 476 mA
Precharge power-down standby current: All device banks idle; Power-
down mode;
t
CK =
t
CK (MIN); CKE = (LOW)
I
DD2P
2
32 32 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN);
CKE = HIGH; Address and other control inputs
changing once per clock cycle;
V
IN
=V
REF
for DQ, DQS, and DM
IDD2F
2
400 400 mA
Active power-down standby current: One device bank active; Power-
down mode;
t
CK =
t
CK (MIN); CKE = LOW
I
DD3P
2
280 240 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle; Address and other control inputs changing once per clock
cycle
I
DD3N
2
480 440 mA
Operating burst read current: Burst = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); Iout = 0mA
I
DD4R
1
736 656 mA
Operating burst write current: Burst = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
I
DD4W
1
736 656 mA
Auto refresh burst current
t
RFC =
t
RFC (MIN)
IDD5
2
1,280 1,280 mA
t
RFC = 7.8125µs
IDD5A
2
48 48 mA
Self refresh current: CKE ≤ 0.2V
I
DD6
2
32 32 mA
Operating bank interleave read current: Four device bank interleaving
reads; (burst = 4) with auto precharge,
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN);
Address and control inputs change only during active READ or WRITE
commands
IDD7
1
1,176 1,096 mA
