CYK256K16SCCB
Document #: 38-05526 Rev. *H Page 4 of 10
AC Test Loads and Waveforms
Parameters 3.0V V
CC
Unit
R1 22000 Ω
R2 22000 Ω
R
TH
11000 Ω
V
TH
1.50 V
Switching Characteristics (Over the Operating Range)
[10]
Parameter Description
–55 –60 –70
UnitMin. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Read Cycle Time 55
[14]
60 70 ns
t
AA
Address to Data Valid 55 60 70 ns
t
OHA
Data Hold from Address Change 5 8 10 ns
t
ACE
CE
1
LOW and CE
2
HIGH to Data Valid 55 60 70 ns
t
DOE
OE LOW to Data Valid 25 25 35 ns
t
LZOE
OE LOW to Low Z
[11, 12]
555ns
t
HZOE
OE HIGH to High Z
[11, 12]
25 25 25 ns
t
LZCE
CE
1
LOW and CE
2
HIGH to
Low Z
[11, 12]
555ns
t
HZCE
CE
1
HIGH and CE
2
LOW to
High Z
[11, 12]
25 25 25 ns
t
DBE
BLE/BHE LOW to Data Valid 55 60 70 ns
t
LZBE
BLE/BHE LOW to Low Z
[11, 12]
555ns
t
HZBE
BLE/BHE HIGH to High-Z
[11, 12]
10 10 25 ns
t
SK
[14]
Address Skew 0 5 10 ns
Write Cycle
[13]
t
WC
Write Cycle Time 55 60 70 ns
t
SCE
CE
1
LOW and CE
2
HIGH to Write End 45 45 60 ns
t
AW
Address Set-up to Write End 45 45 55 ns
t
HA
Address Hold from Write End 0 0 0 ns
t
SA
Address Set-up to Write Start 0 0 0 ns
Notes:
10.Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of V
CC(typ)
/2, input pulse levels of 0V to V
CC(typ),
and output loading of
the specified I
OL
/I
OH
and 30-pF load capacitance
11. t
HZOE
, t
HZCE
, t
HZBE
and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
12.High-Z and Low-Z parameters are characterized and are not 100% tested.
13.The internal write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, CE
2
= V
IH
, BHE and/or BLE =V
IL
. All signals must be ACTIVE to initiate a write
and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates write.
14.To achieve 55-ns performance, the read access should be CE
controlled. In this case t
ACE
is the critical parameter and t
SK
is satisfied when the addresses are
stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle.
VCC VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
TH
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
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