LT3587
20
3587fc
APPLICATIONS INFORMATION
Figure 19. Recommended Component Placement
Figure 18. High Current Paths
Board Layout Consideration
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize effi ciency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential.
In order to minimize magnetic fi eld radiation, reduce the
parasitic inductance by keeping the traces that conduct high
switching currents short, wide and with minimal overall
loop area. These are typically the traces associated with
the switches. Figure 18 outlines the critical paths.
C6
C1
SW1
GND
V
VIN
L1
Q1
CAP1
D
S1
LT3587
C6
C4
SW3
GND
V
VIN
L4
Q3
CAP3
D
S3
LT3587
3587 F18
C6 C7
SW2
GND
V
VIN
V
NEG
L2 L3
Q2
D
S2
LT3587
C2
The voltage signals of the SW1, SW2 and SW3 pins have
rise and fall times of a few ns. Minimize the length and area
of all traces connected to the SW1, SW2 and SW3 pins
to reduce capacitive coupling between these fast nodes
and other circuitry. In particular, keep all the traces of the
feedback voltage pins (FB1, FB2, V
FB3
and I
FB3
) away from
the switching node. Always use a ground plane under the
switching regulator to minimize interplane coupling.
Finally, place as much of the output capacitors of each
channel close to their respective CAP pins. Recommended
component placement is shown in Figure 19.
3587 F19
L4
L3
L2
C7
C2
U1
L1
C1
C4
C6
(OPT)
C6
(OPT)
C6
(OPT)
DS2
DS1
R
FB1
C
FB1
C5
C6
C3
R
IFB3
R
FB2
C
FB2
V
NEG
V
IN
CAP3
V
IN
V
OUT3
V
OUT1
CAP1V
IN
DS3
