LT3587
9
3587fc
OPERATION
All three channels of the LT3587 use a constant frequency,
current mode control scheme to provide voltage and/or
current regulation at the output. Operation can be best un-
derstood by referring to the Block Diagram in Figure 1.
If EN/SS1 is pulled higher than 200mV, the bandgap refer-
ence, the start-up bias and the oscillator are turned on. At
the start of each oscillator cycle, the SR latch X1 is set,
which turns on the power switch Q1. A voltage proportional
to the switch current is added to a stabilizing ramp and
the resulting sum is fed into the positive terminal of the
PWM comparator A3. When this voltage exceeds the level
at the negative input of A3, the SR latch X1 is reset, turning
off the power switch Q1. The level at the negative input
of A3 is set by the error amplifi er A1, which is simply an
amplifi ed version of the difference between the reference
voltage of 1.22V and the feedback voltage. In this manner,
the error amplifi er sets the correct peak switch current
level to keep the output voltage in regulation. If the error
amplifi er output increases, more current is delivered to
the output; if it decreases, less current is delivered.
The second channel is an inverting converter. This channel
is also enabled through the EN/SS1 pin. The basic opera-
tion of this second channel is the same as the positive
channel. The SR latch X2 is also set at the start of each
oscillator cycle. The power switch Q2 is turned on at the
same time as Q1. Q2 turns off based on its own feedback
loop, which consists of error amplifi er A2 and PWM
comparator A4. The reference voltage of this negative
channel is ground.
Voltage clamps (not shown) on the output of the error
amplifi ers A1 and A2 enforce current limit on Q1 and Q2
respectively.
Similar to the fi rst channel, the third channel is also a
positive boost regulator. If EN/SS3 is pulled higher than
200mV, the bandgap reference, the start-up bias and the
oscillators are also turned on. The SR latch X3 is set at
the start of each oscillator cycle which turns on the power
switch Q3. Q3 turns off based on its own feedback loop,
which consists of error amplifi er A5 and PWM comparator
A6. The level at the negative input of A6 is set by the error
amplifi er A5, and is an amplifi ed version of the difference
between the reference voltage of 0.8V and the maximum
of the two feedback voltages at V
FB3
and I
FB3
. A separate
comparator (not shown) sets the maximum current limit
on Q3.
The I
FB3
pin is pulled up internally with a current that
is (1/200) times the load current out of the V
OUT3
pin.
Therefore, an external resistor connected from this pin
to ground generates a feedback voltage proportional to
the V
OUT3
output load current at the I
FB3
pin. When the
voltage at V
FB3
is higher than the voltage at I
FB3
, the third
channel regulates to the feedback voltage at V
FB3
, which in
normal application is a divided down voltage from V
OUT3
.
In this state, the third channel behaves as a boost voltage
regulator. On the other hand if the voltage at I
FB3
is higher,
the third channel regulates to the feedback voltage at I
FB3
,
which therefore regulates the V
OUT3
output load current to
a particular value. In this state, the third channel behaves
as a boost current regulator.
PMOS M1 is used as an output disconnect pass transistor
for the fi rst channel. M1 disconnects the load (V
OUT1
) from
the input as long as the voltage between CAP1 and V
IN
is less than 2.5V (typical) and the voltage between CAP1
and V
OUT1
is less than 10V (typ). Similarly, PMOS M3 is
used as an output disconnect pass transistor for the third
channel. M3 disconnects the load (V
OUT3
) from the input
when the third channel is in shutdown (EN/SS3 voltage
is lower than 200mV) and the voltage between CAP3 and
V
OUT3
is less than 10V (typical).
