102007 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC4519H
Application Information (Cont.)
The junction temperature of the SC4519H can be
further determined by:
totalJAAJ
PθTT +=
θ
JA
is the thermal resistance from junction to ambient.
Its value is a function of the IC package, the application
layout and the air cooling system.
The freewheeling diode also contributes a significant
portion of the total converter loss. This loss should be
minimized to increase the converter efficiency by using
Schottky diodes with low forward drop (V
F
).
D)(1IVP
oFdiode
=
Loop Compensation Design
The SC4519H has an internal error amplifier and requires
a compensation network to connect between the COMP
pin and GND pin as shown in Figure 3. The compensation
network includes C4, C5 and R3. R1 and R2 are used to
program the output voltage according to:
)
R
R
1(8.0V
2
1
O
+=
Assuming the power stage ESR (equivalent series
resistance) zero is an order of magnitude higher than
the closed loop bandwidth, which is typically one tenth of
the switching frequency, the power stage control to output
transfer function with the current loop closed (Ridley
model) for the SC4519H will be as follows:
CR
1
s
1
R5
(s)G
L
L
VD
+
=
Where:
R
L
– Load and
C
– Output capacitor.
The goal of the compensation design is to shape the loop
to have a high DC gain, high bandwidth, enough phase
margin, and high attenuation for high frequency noises.
Figure 3 gives a typical compensation network which
offers 2 poles and 1 zero to the power stage:
BST
1
IN
2
SW
3
GND
4
EN
5
FB
6
COMP
7
SYNC
8
SC4519H
R2
R1
R3
C4
C
D2
L1
C5
Vout
Figure 3. Compensation network provides 2 poles and
1 zero.
The compensation network gives the following
characteristics:
21
2
m
P2
Z
1COMP
RR
R
g
)
ω
s
(1s
ω
s
1
ω(s)G
+
+
+
=
Where:
54
1
CC
1
ω
+
=
43
Z
CR
1
ω
=
543
54
P2
CCR
CC
ω
+
=
The loop gain will be given by:
)
ω
s
(1)
ω
s
(1
ω
s
1
s
1
RR
R
C
R
104.25(s)G(s)GT(s)
P2P1
Z
21
2
4
L
3
VDCOMP
++
+
+
==
Where:
CR
1
ω
L
p1
=
One integrator is added at origin to increase the DC gain.
ω
Z
is used to cancel the power stage pole ω
P1
so that the
loop gain has –20dB/dec rate when it reaches 0dB line.
ω
P2
is placed at half switching frequency to reject high
frequency switching noises. Figure 4 gives the asymptotic
diagrams of the power stage with current loop closed
and its loop gain.
112007 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC4519H
The design guidelines for the SC4519H applications are
as following:
1. Set the loop gain crossover corner frequency ω
C
for
given switching corner frequency ω
C
= 2πf
C
2. Place an integrator at the origin to increase DC and
low frequency gains.
3. Select ω
Z
such that it is placed at ω
P1
to obtain a
-20dB/dec rate to go across the 0dB line.
4. Place a high frequency compensator pole
ω
P2
(ω
P2
= πf
s
) to get the maximum attenuation of
the switching ripple and high frequency noise with
the adequate phase lag at ω
C.
Application Information (Cont.)
Layout Guidelines:
In order to achieve optimal electrical and thermal
performance for high frequency converters, special
attention must be paid to the PCB layouts. The goal of
layout optimization is to identify the high di/dt loops and
minimize them. The following guidelines should be used
to ensure proper operation of the converters.
1. A ground plane is suggested to minimize switching
noises and trace losses and maximize heat
transferring.
2. Start the PCB layout by placing the power components
first. Arrange the power circuit to achieve a clean
power flow route. Put all power connections on one
side of the PCB with wide copper filled areas if
possible.
3. The V
IN
bypass capacitor should be placed next to
the V
IN
and GND pins.
4. The trace connecting the feedback resistors to the
output should be short, direct and far away from any
noise sources such as switching node and switching
components.
5. Minimize the loop including input capacitor, the
SC4519H and freewheeling diode D
2
. This loop
passes high di/dt current. Make sure the trace width
is wide enough to reduce copper losses in this loop.
6. Maximize the trace width of the loop connecting the
inductor, freewheeling diode D
2
and the output
capacitor.
7. Connect the ground of the feedback divider and the
compensation components directly to the GND pin
of the SC4519H by using a separate ground trace.
8. Connect Pin 4 to a large copper area to remove the
IC heat and increase the power capability of the
SC4519H. A few feedthrough holes are required to
connect this large copper area to a ground plane to
further improve the thermal environment of the
SC4519H. The traces attached to other pins should
be as wide as possible for the same purpose.
Mag
ω
C
ω
P2
ω
Z
ω
p1
Loop gain T(s)
Power stage
Figure 4. Asymptotic diagrams of power stage with
current loop closed and its loop gain.
ω
122007 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC4519H
Application Information (Cont.)
Design Example: 16V to 5V at 2A
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314CV52,R7X,5080,n3.3yahsiV
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511D323-DOS,SW8414N1
612D33SS33SS:N/PdlihcriaF
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0113Rk4.3
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%02-/+erasroticapaclladna%1-/+erasrotsiseR
C1
0.22u
SC4519H
BST
1
IN
2
SW
3
GND
4
EN
5
FB
6
COMP
7
SYNC
8
D3
R2
10k
R2
k
R1
R3
3.4k
C4
3.3n
C2
10u
D2
L1
8.2uH
R4
4.75k
C5
180p
V
o
=5V
C3
10u
V
IN
=16V
C1
0.22u
SC4519H
BST
1
IN
2
SW
3
GND
4
EN
5
FB
6
COMP
7
SYNC
8
D3
R2
10k
R2
k
R1
R3
3.4k
C4
3.3n
C2
10u
D2
L1
8.2uH
R4
4.
C1
0.22u
SC4519H
BST
1
IN
2
SW
3
GND
4
EN
5
FB
6
COMP
7
SYNC
8
D3
R2
10k
R2
k
R1
R3
3.4k
C4
3.3n
C2
10u
D2
L1
8.2uH
R4
4.75k
C5
180p
V
o
=5V
C3
10u
V
IN
=16V
52.3k

SC4519HSETRT

Mfr. #:
Manufacturer:
Semtech
Description:
Switching Voltage Regulators 600KHZ 3A STEP-DOWN SW/REG
Lifecycle:
New from this manufacturer.
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