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74VHC595PW,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
74VHC_VHCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 4 July 2012 9 of 22
NXP Semiconductors
74VHC595; 74VHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max
74VHC595
t
pd
propagation
delay
SHCP to Q7S; see Figure 8
[2]
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF - 5.7 13.0 1.0 15.0 1.0 16.5 ns
C
L
= 50 pF - 7.7 16.5 1.0 18.5 1.0 20.1 ns
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF - 4.0 8.2 1.0 9.4 1.0 10.5 ns
C
L
= 50 pF - 5.4 10.0 1.0 11.4 1.0 12.5 ns
STCP to Qn; see Figure 9
[2]
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF - 5.9 11.9 1.0 13.5 1.0 15.0 ns
C
L
= 50 pF - 7.7 15.4 1.0 17.0 1.0 18.5 ns
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF - 4.2 7.4 1.0 8.5 1.0 9.5 ns
C
L
= 50 pF - 5.5 9.0 1.0 10.5 1.0 11.5 ns
MR
to Q7S; see Figure 11
[3]
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF - 5.9 12.8 1.0 13.7 1.0 15.0 ns
C
L
= 50 pF - 7.4 16.3 1.0 17.2 1.0 18.7 ns
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF - 4.4 8.0 1.0 9.1 1.0 10.0 ns
C
L
= 50 pF - 5.6 10.0 1.0 11.1 1.0 12.0 ns
t
en
enable time OE to Qn; see Figure 12
[4]
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF - 5.6 11.5 1.0 13.5 1.0 15.0 ns
C
L
= 50 pF - 7.4 15.0 1.0 17.0 1.0 18.5 ns
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF - 4.0 8.6 1.0 10.0 1.0 11.0 ns
C
L
= 50 pF - 5.3 10.6 1.0 12.0 1.0 13.0 ns
t
dis
disable time OE to Qn; see Figure 12
[5]
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF - 5.4 11.0 1.0 13.0 1.0 14.5 ns
C
L
= 50 pF - 8.7 15.7 1.0 16.2 1.0 17.5 ns
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF - 3.8 8.0 1.0 9.5 1.0 10.5 ns
C
L
= 50 pF - 5.8 10.3 1.0 11.0 1.0 12.0 ns
74VHC_VHCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 4 July 2012 10 of 22
NXP Semiconductors
74VHC595; 74VHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
f
max
maximum
frequency
SHCP or STCP;
see Figure 8 and 9
V
CC
= 3.0 V to 3.6 V 80 125 - 60 - 40 - MHz
V
CC
= 4.5 V to 5.5 V 130 170 - 110 - 90 - MHz
t
W
pulse width SHCP HIGH or LOW;
see Figure 8
V
CC
= 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
V
CC
= 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
STCP HIGH or LOW;
see Figure 9
V
CC
= 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
V
CC
= 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
MR
LOW; see Figure 11
V
CC
= 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns
V
CC
= 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
t
su
set-up time DS to SHCP; see Figure 9
V
CC
= 3.0 V to 3.6 V 3.5 - - 3.5 - 3.5 - ns
V
CC
= 4.5 V to 5.5 V 3.0 - - 3.0 - 3.0 - ns
SHCP to STCP;
see Figure 10
V
CC
= 3.0 V to 3.6 V 8.5 - - 8.5 - 8.5 - ns
V
CC
= 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns
t
h
hold time DS to SHCP; see Figure 10
V
CC
= 3.0 V to 3.6 V 1.5 - - 1.5 - 1.5 - ns
V
CC
= 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - ns
t
rec
recovery
time
MR to SHCP; see Figure 11
V
CC
= 3.0 V to 3.6 V 3.0 - - 3.0 - 3.0 - ns
V
CC
= 4.5 V to 5.5 V 2.5 - - 2.5 - 2.5 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz; V
I
=GNDtoV
CC
[6]
[7]
-180- - - - - pF
74VHCT595; V
CC
= 4.5 V to 5.5 V
t
pd
propagation
delay
SHCP to Q7S; see Figure 8
[2]
C
L
= 15 pF - 3.8 8.2 1.0 9.0 1.0 10.0 ns
C
L
= 50 pF - 5.2 10.0 1.0 11.0 1.0 12.0 ns
STCP to Qn; see Figure 9
[2]
C
L
= 15 pF - 4.0 7.4 1.0 8.5 1.0 9.5 ns
C
L
= 50 pF - 5.3 9.0 1.0 10.5 1.0 11.5 ns
MR
to Q7S; see Figure 11
[3]
C
L
= 15 pF - 4.6 8.2 1.0 9.5 1.0 10.5 ns
C
L
= 50 pF - 5.8 10.5 1.0 11.5 1.0 12.5 ns
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max
74VHC_VHCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 4 July 2012 11 of 22
NXP Semiconductors
74VHC595; 74VHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
[1] Typical values are measured at nominal supply voltage.
[2] t
pd
is the same as t
PHL
and t
PLH
.
[3] t
pd
is the same as t
PHL
only.
[4] t
en
is the same as t
PZL
and t
PZH
.
[5] t
dis
is the same as t
PLZ
and t
PHZ
.
[6] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
V
CC
2
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
[7] All 9 outputs switching.
t
en
enable time OE to Qn; see Figure 12
[4]
C
L
= 15 pF - 4.8 9.0 1.0 11.0 1.0 12.0 ns
C
L
= 50 pF - 6.2 11.6 1.0 13.0 1.0 14.5 ns
t
dis
disable time OE to Qn; see Figure 12
[5]
C
L
= 15 pF - 3.6 6.9 1.0 8.0 1.0 9.0 ns
C
L
= 50 pF - 5.8 10.3 1.0 11.0 1.0 12.0 ns
f
max
maximum
frequency
SHCP and STCP;
see Figure 8
and 9
130 170 - 110 - 90 - MHz
t
W
pulse width SHCP HIGH or LOW;
see Figure 8
5.0 - - 5.0 - 5.0 - ns
STCP HIGH or LOW;
see Figure 9
5.0 - - 5.0 - 5.0 - ns
MR
LOW; see Figure 11 5.0 - - 5.0 - 5.0 - ns
t
su
set-up time DS to SHCP; see Figure 9 3.0 - - 3.0 - 3.0 - ns
SHCP to STCP;
see Figure 10
5.0 - - 5.0 - 5.0 - ns
t
h
hold time DS to SHCP; see Figure 10 2.0 - - 2.0 - 2.0 - ns
t
rec
recovery
time
MR to SHCP; see Figure 11 3.0 - - 3.0 - 3.0 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz; V
I
=GNDtoV
CC
[6]
[7]
-190- - - - - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

74VHC595PW,118

Mfr. #:
Buy 74VHC595PW,118
Manufacturer:
Nexperia
Description:
Counter Shift Registers 8bit 7V 1CIRC
Lifecycle:
New from this manufacturer.
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