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74VHC595PW,118
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P23
74VHC_VHCT595
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 2012. All rights reserv
ed.
Product data sheet
Rev
. 2 — 4 July 2012
12 of 22
NXP Semiconductors
74VHC595; 74VHCT595
8-bit serial-in/serial
-o
ut or p
arallel-out shif
t register with output latches
12. W
aveforms
Measurement points are given in
T
able 8
.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 8.
Shift clock pulse, maximum frequency and input to outpu
t propagation delays
mna557
SH
CP
input
Q
7
S output
t
PLH
t
PHL
t
W
1/
f
max
V
M
V
OH
V
I
GND
V
OL
V
M
Measurement points are given in
T
able 8
.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 9.
Storage clock t
o output prop
agation delays
mna558
ST
CP
input
Q
n
output
t
PLH
t
PHL
t
W
t
su
1/
f
max
V
M
V
OH
V
I
GND
V
OL
V
M
SH
CP
input
V
I
GND
V
M
74VHC_VHCT595
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 2012. All rights reserv
ed.
Product data sheet
Rev
. 2 — 4 July 2012
13 of 22
NXP Semiconductors
74VHC595; 74VHCT595
8-bit serial-in/serial
-o
ut or p
arallel-out shif
t register with output latches
Measurement points are given in
T
able 8
.
The shaded areas indicate when the input is per
mitted to change for predictable output performance.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 10.
Dat
a set-up and hold times
mna560
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
I
V
OH
V
OL
V
I
Q
7
S output
SH
CP
input
D
S
input
Measurement points are given in
T
able 8
.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 1
1.
Master rese
t to output pr
opagation delays
mna561
MR
input
SH
CP
input
Q
7
S output
t
PHL
t
W
t
rec
V
M
V
OH
V
OL
V
I
GND
V
I
GND
V
M
V
M
74VHC_VHCT595
All informatio
n provided in thi
s document is su
bject to legal
disclaimers.
© NXP B.V
. 2012. All rights reserv
ed.
Product data sheet
Rev
. 2 — 4 July 2012
14 of 22
NXP Semiconductors
74VHC595; 74VHCT595
8-bit serial-in/serial
-o
ut or p
arallel-out shif
t register with output latches
Measurement points are given in
T
able 8
.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 12.
Enable an
d disable times
mna450
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
OH
−
0.3
V
V
OL
+ 0.3
V
outputs
enabled
output
LOW
-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
V
I
V
CC
V
M
V
OL
V
OH
GND
GND
t
PZL
t
PZH
V
M
V
M
T
able 8.
Mea
surement points
Ty
p
e
Input
Output
V
M
V
M
74VHC595
0.5V
CC
0.5V
CC
74VHCT595
1.5 V
0.5V
CC
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P23
74VHC595PW,118
Mfr. #:
Buy 74VHC595PW,118
Manufacturer:
Nexperia
Description:
Counter Shift Registers 8bit 7V 1CIRC
Lifecycle:
New from this manufacturer.
Delivery:
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