IS61C1024
IS61C1024L
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
SR028-1K
05/12/99
ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range, Standard and Low Power)
-12 ns
(3)
-15 ns -20 ns -25 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 12 — 15 — 20 — 25 — ns
tSCE1 to Write End 10 — 12 — 15 — 20 — ns
tSCE2 CE2 to Write End 10 — 12 — 15 — 20 — ns
tAW Address Setup Time to Write End 10 — 12 — 15 — 20 — ns
tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWE
(4)
Pulse Width 10 — 10 — 12 — 15 — ns
tSD Data Setup to Write End 7 — 8 — 10 — 12 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
tHZWE
(5)
LOW to High-Z Output — 7 — 7 — 10 — 12 ns
tLZWE
(5)
HIGH to Low-Z Output 2 — 2 — 2 — 2 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. The internal write time is defined by the overlap of LOW, CE2 HIGH and LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. -12 ns device for IS61C1024 only.
4. Tested with HIGH.
5. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
