IDT72V70810 REVISION A JUNE 9, 2014 18 ©2014 Integrated Device Technology, Inc.
IDT 72V70810 Data Sheet 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024
Figure 12. Multiplexed Bus Timing (Intel Mode)
AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (INTEL)
NOTE:
1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
Symbol Parameter Min. Typ. Max. Units Test Conditions
t
ALW ALE Pulse Width 20 ns
t
ADS Address Setup from ALE falling 3 ns
t
ADH Address Hold from ALE falling 3 ns
t
ALRD RD Active after ALE falling 3 ns
t
DDR Data Setup from DTA LOW on Read 5 ns CL = 150pF
t
CSRW CS Hold after RD/WR 5 ns
t
RW RD Pulse Width (Fast Read) 45 ns
t
CSR
CS Setup from RD 0 ns
t
DHR
(1)
Data Hold after RD 10 20 ns CL = 150pF, RL = 1K
t
WW WR Pulse Width (Fast Write) 45 ns
t
ALWR WR Delay after ALE falling 3 ns
t
CSW CS Setup from WR 0 ns
t
DSW Data Setup from WR (Fast Write) 20 ns
t
SWD Valid Data Delay on Write (Slow Write) 122 ns
t
DHW Data Hold after WR Inactive 5 ns
t
AKD Acknowledgment Delay:
Reading/Writing Registers 43/43 ns C
L = 150pF
Reading/Writing Memory 220/210 ns C
L = 150pF
t
AKH
(1)
Acknowledgment Hold Time 22 ns CL = 150pF, RL = 1K
