IDT72V70810 REVISION A JUNE 9, 2014 9 ©2014 Integrated Device Technology, Inc.
IDT 72V70810 Data Sheet 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 1,024 x 1,024
TABLE 6 — INTERFACE MODE SELECTION (IMS) REGISTER BITS
Read/Write Address: 01H,
Reset Value: 0000H.
Bit Name Description
15-10 Unused Must be zero for normal operation.
9-5 BPD4-0
(Block Programming Data)
These bits carry the value to be loaded into the connection memory block whenever the memory block
programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set
to 1, the contents of the bits BPD4-0 are loaded into bit 15 and 11 of the connection memory. Bit 10 to bit 0
of the connection memory are set to 0.
4 BPE
(Begin Block Programming Enable)
A zero to one transition of this bit enables the memory block programming function. The BPE and BPD4-0
bits in the IMS register have to be defi ned in the same write operation. Once the BPE bit is set HIGH,
the device requires two frames to complete the block programming. After the programming function has
fi nished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE
or MBP can be set to 0 to abort to ensure proper operation. When BPE = 1, the other bit in the IMS register
must not be changed for two frames to ensure proper operation.
3 OSB
(Output Stand By)
When ODE = 0 and OSB = 0, the output drivers of TX0 to TX7 are in high impedance mode. When ODE
= 0 and OSB = 1, the output driver of TX0 to TX7 function normally. When ODE = 1, TX0 to TX7 output
drivers function normally.
2 SFE
(Start Frame Evaluation)
A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR
register changes from zero to one, the evaluation procedure stops. To start another fame evaluation
1-0 Unused For normal operation, bit 1 = 1 and bit 0 = 0.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 BPD4 BPD3 BPD2 BPD1 BPD0 BPE OSB SFE 1 0
TABLE 5 — CONTROL REGISTER (CR) BITS
Read/Write Address: 00H,
Reset Value: 0000
H.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 MBP MS 0 STA2 STA1 STA0
Bit Name Description
15-6 Unused Must be zero for normal operation.
5 MBP
(Memory Block Program)
When 1, the connection memory block programming feature is ready for the programming of Connection Memory high bits,
bit 11 to bit 15. When 0, this feature is disabled.
4MS
(Memory Select)
When 0, connection memory is selected for read or write operations. When 1, the data memory is selected for read oper-
ations and connection memory is selected for write operations. (No microprocessor write operation is allowed for the data
memory.)
3 Unused Must be zero for normal operation.
2-0 STA2-0
(Stream Address Bits)
The binary value expressed by these bits refers to the input or output data stream, which corresponds to the subsection of
memory made accessible for subsequent operations. (STA2 = MSB, STA0 = LSB)
