AD7660ASTZ Datasheet AD7660ASTZ, AD7660ASTZRL, AD7660ACPZRL | P13-P15

REV. E

AD7660

–12–

Analog Input

Figure 6 shows an equivalent circuit of the input structure of the

AD7660.

OR INGND

AGND

AVDD

Figure 6. Equivalent Analog Input Circuit

The two diodes D1 and D2 provide ESD protection for the

analog inputs IN and INGND. Care must be taken to ensure that

the analog input signal never exceeds the supply rails by more than

0.3 V. This will cause these diodes to become forward-biased and

start conducting current. These diodes can handle a forward-

biased current of 100 mA maximum. For instance, these

conditions could eventually occur when the input buffer’s (U1)

supplies are different from AVDD. In such cases, an input buffer

with a short circuit current limitation can be used to protect the part.

This analog input structure allows the sampling of the differential

signal between IN and INGND. Unlike other converters, the

INGND input is sampled at the same time as the IN input. By

using this differential input, small signals common to both inputs

are rejected as shown in Figure 7, which represents the typical

CMRR over frequency. For instance, by using INGND to sense

a remote signal ground, difference of ground potentials between

the sensor and the local ADC ground is eliminated.

FREQUENCY – Hz

CMRR – dB

10k 10M1k 1M

100k

Figure 7. Analog Input CMRR vs. Frequency

During the acquisition phase, the impedance of the analog input

IN can be modeled as a parallel combination of capacitor C1 and

the network formed by the series connection of R1 and C2.

Capacitor C1 is primarily the pin capacitance. The resistor R1 is

typically 3242 W and is a lumped component made up of some

serial resistors and the on resistance of the switches. The capacitor

C2 is typically 60 pF and is mainly the ADC sampling capacitor.

During the conversion phase, where the switches are opened, the

input impedance is limited to C1. It has to be noted that the input

impedance of the AD7660, unlike other SAR ADCs, is not a pure

capacitance and thus, inherently reduces the kickback transient at

the beginning of the acquisition phase. The R1, C2 makes a one-

pole low-pass filter with a typical cutoff frequency of 820 kHz that

reduces undesirable aliasing effect and limits the noise.

When the source impedance of the driving circuit is low, the

AD7660 can be driven directly. Large source impedances will

significantly affect the ac performances, especially the total

harmonic distortion (THD). The maximum source impedance

depends on the amount of THD that can be tolerated. The

THD degrades in function of the source impedance and the

maximum input frequency as shown in Figure 8.

INPUT FREQUENCY – kHz

–100

1 10010

THD – dB

–95

–90

–85

–80

–75

–70

= 500

= 100

= 50

= 20

Figure 8. THD vs. Analog Input Frequency and

Source Resistance

Driver Amplifier Choice

Although the AD7660 is easy to drive, the driver amplifier needs

to meet at least the following requirements:

•

The driver amplifier and the AD7660 analog input circuit

must be able, together, to settle for a full-scale step of

the capacitor array at a 16-bit level (0.0015%). For

instance, operation at the maximum throughput of 100 kSPS

requires a minimum gain bandwidth product of 5 MHz.

•

The noise generated by the driver amplifier needs to be

kept as low as possible in order to preserve the SNR and

transition noise performance of the AD7660. The noise

coming from the driver is filtered by the AD7660 analog

input circuit one-pole low-pass filter made by R1 and C2.

For instance, a driver with an equivalent input noise of

4 nV/÷Hz like the OP184 and configured as a buffer, thus

with a noise gain of +1, degrades the SNR by only 0.1 dB.

•

The driver needs to have a THD performance suitable to

that of the AD7660. TPC 8 gives the THD versus frequency

that the driver should preferably exceed.

The SNR degradation due to the amplifier is:

SNR

fNe

LOSS

dB N

784

log

()

–

where:

–3 dB

is the –3 dB input bandwidth in MHz of the AD7660

(0.82 MHz) or the cutoff frequency of the input filter if any

are used.

N is the noise factor of the amplifier (1 if in buffer configuration).

is the equivalent input noise voltage of the op amp in

nV/÷Hz.

REV. E

AD7660

–13–

The AD8519, OP162, or the OP184 meet these requirements

and are usually appropriate for almost all applications. As an

alternative, in very high speed and noise-sensitive applications,

the AD8021 with an external compensation capacitor of 10 pF

or the AD829 with an external compensation capacitor of 82 pF

can be used. This capacitor should have good linearity as an

NPO ceramic or mica type. Moreover, the use of a noninverting

+1 gain arrangement is recommended and helps to obtain the

best signal-to-noise ratio.

Voltage Reference Input

The AD7660 uses an external 2.5 V voltage reference.

The voltage reference input REF of the AD7660 has a dynamic

input impedance; it should therefore be driven by a low impedance

source with an efficient decoupling between REF and REFGND

inputs. This decoupling depends on the choice

of the voltage

reference but usually consists of a 1 mF

ceramic capacitor and a

low ESR tantalum capacitor connected to the REF and REFGND

inputs with minimum parasitic inductance. 47 mF is an appropriate

value for the tantalum capacitor when used with one of the

recommended reference voltages:

∑ The low noise, low temperature drift ADR421 and AD780

voltage references

∑ The low power ADR291 voltage reference

∑ The low cost AD1582 voltage reference

For applications using multiple AD7660s, it is more effective to

buffer the reference voltage with a low noise, very stable op amp

like the AD8031.

Care should also be taken with the reference temperature coeffi-

cient of the voltage reference that directly affects the full-scale

accuracy if this parameter matters. For instance, a ± 15 ppm/∞C

tempco of the reference changes the full scale by ± 1 LSB/∞C.

REF

, as mentioned in the specification table, could be increased

to AVDD – 1.85 V. The benefit here is the increased SNR

obtained as a result of this increase. Since the input range is

defined in terms of V

REF

, this would essentially increase the

range to make it a ±3 V input range with an AVDD above 4.85 V.

The theoretical improvement as a result of this increase in

reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical

quantization noise, however, the observed improvement is

approximately 1 dB. The AD780 can be selected with a 3 V

reference voltage.

Power Supply

The AD7660 uses three sets of power supply pins: an analog 5 V

supply AVDD, a digital 5 V core supply DVDD, and a digital

input/output interface supply OVDD. The OVDD supply allows

direct interface with any logic working between 2.7 V and 5.25 V.

To reduce the number of supplies needed, the digital core

(DVDD) can be supplied through a simple RC filter from the

analog supply, as shown in Figure 5. The AD7660 is independent

of power supply sequencing and thus free from supply voltage

induced latch-up. Additionally, it is very insensitive to power supply

variations over a wide frequency range, as shown in Figure 9.

INPUT FREQUENCY – Hz

PSRR – dB

–80

1k 10k 100k 1M

–75

–70

–65

–60

–55

–50

Figure 9. PSRR vs. Frequency

POWER DISSIPATION VS. THROUGHPUT

The AD7660 automatically reduces its power consumption at

the end of each conversion phase. During the acquisition phase,

the operating currents are very low, which allows a significant

power saving when the conversion rate is reduced, as shown in

Figure 10. This feature makes the AD7660 ideal for very low

power battery applications. It should be noted that the digital

interface remains active even during the acquisition phase. To

reduce the operating digital supply currents even further, the

digital inputs need to be driven close to the power rails (i.e.,

DVDD and DGND for all inputs except EXT/INT, INVSYNC,

INVSCLK, RDC/SDIN, and OVDD or OGND for the last

four inputs.

THROUGHPUT – SPS

10 100000

POWER DISSIPATION – W

100000

1000

10000

100

100 1000 10000

Figure 10. Power Dissipation vs. Sample Rate

REV. E

AD7660

–14–

CONVERSION CONTROL

Figure 11 shows the detailed timing diagrams of the conversion

process. The AD7660 is controlled by the signal CNVST, which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the conver-

sion is complete. The CNVST signal operates independently of

CS and RD signals.

CNVST

BUSY

MODE

ACQUIRE CONVERT ACQUIRE CONVERT

Figure 11. Basic Conversion Timing

For a true sampling application, the recommended operation of

the CNVST signal is the following:

CNVST must be held HIGH from the previous falling edge

of BUSY, and during a minimum delay corresponding to the

acquisition time t

; then, when CNVST is brought LOW, a

conversion is initiated and the BUSY signal goes HIGH until

the completion of the conversion. Although CNVST is a digital

signal, it should be designed with special care with fast, clean

edges and levels, with minimum overshoot and undershoot or

ringing. For applications where the SNR is critical, the CNVST

signal should have a very low jitter. This may be achieved by

using a dedicated oscillator for CNVST generation or, at least,

to clock it with a high frequency low jitter clock, as shown in

Figure 5.

RESET

DATABUS

BUSY

CNVST

Figure 12. RESET Timing

For other applications, conversions can be automatically initiated.

If CNVST is held LOW when BUSY is LOW, the AD7660

controls the acquisition phase and then automatically initiates a

new conversion. By keeping CNVST LOW, the AD7660 keeps

the conversion process running by itself. It should be noted that

the analog input has to be settled when BUSY goes LOW. Also,

at power-up, CNVST should be brought LOW once to initiate

the conversion process. In this mode, the AD7660 could some-

times run slightly faster than the guaranteed limit of 100 kSPS.

DIGITAL INTERFACE

The AD7660 has a versatile digital interface; it can be interfaced

with the host system by using either a serial or parallel interface.

The serial interface is multiplexed on the parallel data bus. The

AD7660 digital interface also accommodates both 3 V or 5 V

logic by simply connecting the OVDD supply pin of the AD7660

to the host system interface digital supply. Finally, by using the

OB/2C input pin, both twos complement or straight binary

coding can be used.

The two signals CS and RD control the interface. CS and RD

have a similar effect because they are together internally. When

at least one of these signals is HIGH, the interface outputs are

in high impedance. Usually, CS allows the selection of each

AD7660 in multicircuit applications and is held LOW in a

single AD7660 design. RD is generally used to enable the con-

version result on the data bus.

CNVST

BUSY

ATA BUS

CS = RD = 0

PREVIOUS CONVERSION DATA NEW DATA

Figure 13. Master Parallel Data Timing for Reading

(Continuous Read)

PARALLEL INTERFACE

The AD7660 is configured to use the parallel interface when the

SER/PAR is held LOW. The data can be read either after each

conversion, which is during the next acquisition phase, or during

the following conversion as shown, respectively, in Figures 14 and

15. When the data is read during the conversion, however, it is

recommended that it is read-only during the first half of the

conversion phase. This avoids any potential feedthrough be

tween

voltage transients on the digital interface and the most critical

analog conversion circuitry.

CURRENT

CONVERSION

BUSY

DATA BUS

Figure 14. Slave Parallel Data Timing for Reading

(Read after Convert)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD7660ASTZ

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Description:

Analog to Digital Converters - ADC 16B 100kSPS CMOS Successive Approx

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AD7660ASTZ

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