SC16C2550B_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 12 January 2009 15 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7. Register descriptions
Table 8 details the assigned bit functions for the SC16C2550B internal registers. The
assigned bit functions are more fully defined in Section 7.1 through Section 7.10.
[1] The value shown represents the register’s initialized hexadecimal value; X = not applicable.
[2] Accessible only when LCR[7] is logic 0.
[3] Baud rate registers accessible only when LCR[7] is logic 1.
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 through D0)
to the TSR and UART via the THR, providing that the THR is empty. The THR empty flag
in the LSR register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2550B and
receive FIFO by reading the RHR register. The receive section provides a mechanism to
Table 8. SC16C2550B internal registers
A2 A1 A0 Register Default
[1]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
General register set
[2]
0 0 0 RHR XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0 0 0 THR XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0 0 1 IER 00 0 0 0 0 modem
status
interrupt
receive
line
status
interrupt
transmit
holding
register
interrupt
receive
holding
register
0 1 0 FCR 00 RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
reserved
0
reserved
0
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFOs
enable
0 1 0 ISR 01 FIFOs
enabled
FIFOs
enabled
0 0 INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0 1 1 LCR 00 divisor
latch
enable
set break set parity even
parity
parity
enable
stop bits word
length
bit 1
word
length
bit 0
1 0 0 MCR 00 0 0 0 loop
back
OP2/INT
enable
(OP1) RTS DTR
1 0 1 LSR 60 FIFO
data
error
THR and
TSR
empty
THR
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1 1 0 MSR X0 CD RI DSR CTS ∆CD ∆RI ∆DSR ∆CTS
1 1 1 SPR FF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Special register set
[3]
0 0 0 DLL XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0 0 1 DLM XX bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
