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SC16C2550BIB48,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
SC16C2550B_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 12 January 2009 25 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
8. Limiting values
9. Static characteristics
[1] Except XTAL2, V
OL
= 1 V typical.
Table 23. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage - 7 V
V
n
voltage on any other pin at D7 to D0 pins GND − 0.3 V
CC
+ 0.3 V
at input only pins GND − 0.3 5.3 V
T
amb
operating temperature −40 +85 °C
T
stg
storage temperature −65 +150 °C
P
tot
/pack total power dissipation per package - 500 mW
Table 24. Static characteristics
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
CC
±
10 %; unless otherwise specified.
Symbol Parameter Conditions V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5.0 V Unit
Min Max Min Max Min Max
V
IL(clk)
clock LOW-level input voltage −0.3 +0.45 −0.3 +0.6 −0.5 +0.6 V
V
IH(clk)
clock HIGH-level input voltage 1.8 V
CC
2.4 V
CC
3.0 V
CC
V
V
IL
LOW-level input voltage except X1 clock −0.3 +0.65 −0.3 +0.8 −0.5 +0.8 V
V
IH
HIGH-level input voltage except X1 clock 1.6 - 2.0 - 2.2 - V
V
OL
LOW-level output voltage on all outputs
[1]
I
OL
=5mA
(data bus)
-----0.4V
I
OL
=4mA
(other outputs)
---0.4--V
I
OL
=2mA
(data bus)
-0.4----V
I
OL
= 1.6 mA
(other outputs)
-0.4----V
V
OH
HIGH-level output voltage I
OH
= −5mA
(data bus)
----2.4-V
I
OH
= −1mA
(other outputs)
- - 2.0 - - - V
I
OH
= −800 µA
(data bus)
1.85 - - - - - V
I
OH
= −400 µA
(other outputs)
1.85 - - - - - V
I
LIL
LOW-level input leakage current - ±10 - ±10 - ±10 µA
I
L(clk)
clock leakage current - ±30 - ±30 - ±30 µA
I
CC
supply current f = 5 MHz - 3.5 - 4.5 - 4.5 mA
C
i
input capacitance - 5 - 5 - 5 pF
SC16C2550B_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 12 January 2009 26 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
10. Dynamic characteristics
Table 25. Dynamic characteristics
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
CC
±
10 %; unless otherwise specified.
Symbol Parameter Conditions V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5.0 V Unit
Min Max Min Max Min Max
t
w1
clock pulse duration 10 - 6 - 6 - ns
t
w2
clock pulse duration 10 - 6 - 6 - ns
f
XTAL
oscillator/clock frequency
[1][2]
- 48 - 80 80 MHz
t
6s
address set-up time 0 - 0 - 0 - ns
t
6h
address hold time 0 - 0 - 0 - ns
t
7d
IOR delay from chip select 10 - 10 - 10 - ns
t
7w
IOR strobe width 25 pF load 77 - 26 - 23 - ns
t
7h
chip select hold time from
IOR
0-0-0-ns
t
9d
read cycle delay 25 pF load 20 - 20 - 20 - ns
t
12d
delay from IOR to data 25 pF load - 77 - 26 - 23 ns
t
12h
data disable time 25 pF load - 15 - 15 - 15 ns
t
13d
IOW delay from chip select 10 - 10 - 10 - ns
t
13w
IOW strobe width 20 - 20 - 15 - ns
t
13h
chip select hold time from
IOW
0-0-0-ns
t
15d
write cycle delay 25 - 25 - 20 - ns
t
16s
data set-up time 20 - 20 - 15 - ns
t
16h
data hold time 15 - 5 - 5 - ns
t
17d
delay from IOW to output 25 pF load - 100 - 33 - 29 ns
t
18d
delay to set interrupt from
Modem input
25 pF load - 100 - 24 - 23 ns
t
19d
delay to reset interrupt from
IOR
25 pF load - 100 - 24 - 23 ns
t
20d
delay from stop to set
interrupt
[3]
-T
RCLK
-T
RCLK
-T
RCLK
s
t
21d
delay from IOR to reset
interrupt
25 pF load - 100 - 29 - 28 ns
t
22d
delay from start to set
interrupt
- 100 - 45 - 40 ns
t
23d
delay from IOW to transmit
start
[3]
8T
RCLK
24T
RCLK
8T
RCLK
24T
RCLK
8T
RCLK
24T
RCLK
s
t
24d
delay from IOW to reset
interrupt
- 100 - 45 - 40 ns
t
25d
delay from stop to set
RXRDY
[3]
-T
RCLK
-T
RCLK
-T
RCLK
s
t
26d
delay from IOR to reset
RXRDY
- 100 - 45 - 40 ns
t
27d
delay from IOW to set
TXRDY
- 100 - 45 - 40 ns
SC16C2550B_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 12 January 2009 27 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2] Maximum frequency =
[3] RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.
[4] Reset pulse must happen when these signals are inactive: CS, IOW, IOR.
10.1 Timing diagrams
t
28d
delay from start to reset
TXRDY
[3]
-8T
RCLK
-8T
RCLK
-8T
RCLK
s
t
RESET
RESET pulse width
[4]
200 - 40 - 40 - ns
N baud rate divisor 1 (2
16
− 1)1(2
16
− 1) 1 (2
16
− 1)
Table 25. Dynamic characteristics
…continued
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
CC
±
10 %; unless otherwise specified.
Symbol Parameter Conditions V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5.0 V Unit
Min Max Min Max Min Max
1
t
w3
-------
Fig 8. General write timing
data
active
active
valid
address
002aae279
A0 to A2
CSA, CSB
IOW
D0 to D7
t
16s
t
16h
t
13d
t
13w
t
15d
t
6h
t
13h
t
6s
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SC16C2550BIB48,151

Mfr. #:
Buy SC16C2550BIB48,151
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC 2CH. UART 16B FIFO
Lifecycle:
New from this manufacturer.
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